Analog Design Engineer for PLL/Adaptive Clocking

Senior analog design engineer to define, specify, and implement current and future advanced PLL IPs for AMD products. Role includes architecture development, transistor-level design, pre-tapeout verification, and mentoring of junior engineers in a hybrid San Diego setting.

• Design of complex PLL building blocks including architecture development and transistor-level circuit design
• Run pre-tapeout verification flows to confirm design meets performance, power, reliability and timing requirements
• Work closely with mask design engineers to deliver the physical design as well as define production/bench-level test plans with post-silicon characterization groups for silicon evaluation to ensure interlocked and high-quality execution
• Lead/mentor junior engineers
• Run Monte-Carlo, noise, aging, EM and IR drop simulations and stability analysis

Focus on mixed-signal PLL design in FinFET with blocks like VCO, charge pump, dividers, TDC, bandgap; uses Cadence ADE-L/ADE-XL, Monte-Carlo, and various SPICE tools (Spectre, Hspice); includes physical design and STA; requires scripting (Tcl, Python) and verification (DRC/LVS with Calibre).

The ideal candidate is a senior analog design engineer with strong mixed-signal PLL experience in FinFET, adept with Cadence tools, and capable of leading junior engineers. They should excel in transistor-level design, pre-tapeout verification, and cross-functional collaboration to deliver high-quality PLL IPs.