Position Details

Type Full-Time

Experience mid

Exp. Years 3+ years

Education Not specified

Category Software Engineering

About this role

This role involves designing GPU and ML shader cores, focusing on micro-architecture, RTL implementation, and optimizing performance, power, and area for next-generation products.

Key Responsibilities

Collaborate with architects and verification engineers
Define and document micro-architecture
Implement RTL and deliver verified design
Assist in debugging and performance analysis
Work with Physical Design team

Technical Overview

The position requires expertise in Verilog, ASIC design flow, GPU/ML pipelines, and physical design, working closely with cross-disciplinary teams to deliver verified, high-performance IP.

Ideal Candidate

The ideal candidate is a mid-level ASIC design engineer with 3+ years of experience in GPU and ML shader core development, proficient in Verilog and ASIC design flow, with strong collaboration and problem-solving skills.

Must-Have Skills

micro-architectureRTL developmentVerilogASIC design flowGPU/ML/AI pipelines

Nice-to-Have Skills

GPU/CPU/ML/AI pipelinesinterconnect networkscachesschedulingsynchronization

Tools & Platforms

VerilogASIC design toolsPhysical Design tools

Required Skills

VerilogRTLASIC design flowmicro-architectureGPUMLShader CoreDesign cyclePower analysisTiming analysis

Hard Skills

VerilogRTLASIC design flowmicro-architectureGPUMLAIShader CoreMicro-architectingDesign cycleTiming analysisPower analysisPerformance targetsDebuggingPhysical Design

Soft Skills

collaborationinterpersonal skillsteamworkproblem-solvinginnovative thinking

Industry & Role

Industry Semiconductors & Hardware

Job Function Design and develop GPU/ML shader core ASICs

Role Subtype Systems Engineer

Tech Domains Active Directory, Microsoft 365, Azure, Amazon Web Services, Kubernetes, Docker, Python, Java, SQL / PostgreSQL, Cybersecurity

Keywords for Your Resume

ASIC Design EngineerGPUMLShader CoreVerilogRTLmicro-architectureASIC design flowGPU pipelinesPower analysisTiming analysisDebuggingPhysical DesignDesign cyclePerformance targets

Deal Breakers

Lack of ASIC or GPU design experience, No Verilog or RTL development experience, Inability to work in a hybrid environment

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ASIC Design Engineer, GPU/ML Shader Core

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