Position Details

Type Not Specified

Experience mid

Exp. Years Not specified

Education Not specified

Category Software Engineering

About this role

This role involves designing and implementing high-performance ASIC chips, integrating subsystems, and ensuring design quality through verification and analysis.

Key Responsibilities

Integrate subsystems into SOC
Implement RTL in SystemVerilog
Perform timing and quality checks
Analyze design trade-offs
Collaborate with teams

Technical Overview

Focus on ASIC hardware design using SystemVerilog, RTL development, synthesis, timing analysis, and verification processes.

Ideal Candidate

The ideal candidate is a mid-level ASIC design engineer with experience in SystemVerilog, RTL development, and verification processes. They should have strong debugging skills and familiarity with microarchitecture and synthesis tools.

Must-Have Skills

Implement and deliver high performance RTLAnalyze design and microarchitectureDevelop micro-architectureImplement SystemVerilog RTLPerform lint and clock domain crossing checks

Nice-to-Have Skills

Scripting in PythonAssertions proficiencyRTL test failure analysis

Tools & Platforms

SystemVerilogRTLSynthesis toolsTiming analysis tools

Required Skills

ASIC designSystemVerilogRTLsynthesistiming analysisassertionsPythonmicroarchitectureclock domain crossingDFT

Hard Skills

SystemVerilogRTLSynthesisTiming AnalysisAssertionsPythonMicroarchitectureClock Domain CrossingDFTVerification

Soft Skills

Debug SkillsAnalytical ThinkingCollaborationLearning Mindset

Industry & Role

Industry Technology / Cloud Computing / Machine Learning

Job Function ASIC hardware design and verification

Role Subtype Hardware Design Engineer

Tech Domains Active Directory, Microsoft 365, Azure, Amazon Web Services, Linux

Keywords for Your Resume

ASIC Design EngineerSystemVerilogRTLSynthesisTiming analysisAssertionsPythonMicroarchitectureClock domain crossingDFTVerificationASICSOCHardware designMicroarchitecture designRTL implementationASIC designsynthesistiming analysisassertionsmicroarchitectureclock domain crossing

Deal Breakers

Lack of experience with SystemVerilog or RTL, No microarchitecture background, No scripting in Python, No ASIC design experience

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