Position Details

Salary $91K – $152K USD / year

Type Full-Time

Experience senior

Exp. Years 8+ years

Education BSEE + 8+ years of related experience, or MSEE + 6+ years of experience

Category QA & Testing

About this role

This role involves verifying high-speed ASIC designs using industry-standard methodologies and tools, focusing on PCIe interfaces and data path verification.

Key Responsibilities

Verify ASIC designs using System Verilog and UVM
Ensure coverage closure
Develop verification environments
Work on PCIe and data path verification
Lead verification efforts

Technical Overview

The technical environment includes System Verilog, UVM, VCS/Incisive simulation tools, with a focus on constrained random verification, coverage analysis, and PCIe protocol verification.

Ideal Candidate

The ideal candidate is a senior ASIC verification engineer with 8+ years of experience in hardware verification, proficient in System Verilog and UVM, with strong knowledge of PCIe interfaces and verification methodologies. They should be self-motivated, capable of technical leadership, and experienced in constrained random verification and coverage closure.

Must-Have Skills

System VerilogUVMCoverage closureConstrained random verification methodologiesExperience with PCIeStrong understanding of datapath flows

Nice-to-Have Skills

SVOOP3rd party BFMPythonPerl

Tools & Platforms

VCSIncisivePythonPerl

Required Skills

System VerilogUVMVCSIncisivePythonPerlConstrained random verificationCoverage closurePCIeData path flows

Hard Skills

System VerilogUVMVCSIncisivePythonPerlConstrained random verification methodologiesCoverage closureOOPPCIeData path flows

Soft Skills

Self motivatedTeamworkTechnical leadershipCommunicationProblem-solving

Industry & Role

Industry Semiconductor/Hardware

Job Function ASIC Design Verification Engineer

Keywords for Your Resume

ASIC Design VerificationSystem VerilogUVMCoverage closureConstrained random verificationPCIeData path flowsVCSIncisivePythonPerlOOPVerification methodologiesRTL verificationHardware verificationSimulation tools

Deal Breakers

Less than 6 years of ASIC verification experience, Lack of experience with System Verilog or UVM, No experience with PCIe or data path verification, Inability to work independently in verification teams

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