Position Details
About this role
This role involves verifying high-speed ASIC designs, focusing on Ethernet and host interfaces, using industry-standard methodologies like constrained random verification with SystemVerilog and UVM.
Key Responsibilities
- Verify ASIC designs
- Develop constrained random testbenches
- Achieve coverage closure
- Collaborate with design teams
- Ensure design correctness
Technical Overview
The position requires expertise in SystemVerilog, UVM, simulation tools (VCS, Incisive), scripting (Python, Perl), and verification of data path and high-speed interfaces such as PCIe.
Ideal Candidate
The ideal candidate is an experienced ASIC verification engineer with 8+ years of experience, proficient in SystemVerilog, UVM, and simulation tools like VCS and Incisive. Strong understanding of data path verification, Ethernet protocols, and constrained random methodologies is essential.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 6 years of relevant experience, Lack of proficiency in SystemVerilog or UVM, No experience with verification tools like VCS or Incisive, Inability to work on Ethernet or host interface verification
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