Position Details

Salary $44K – $185K USD / year

Type Internship

Experience intern

Exp. Years 0

Education Currently enrolled in a full-time undergraduate program

Category Software Engineering

About this role

ASIC Design Verification Intern to contribute to next-generation 100G-1T coherent optical communications products, focusing on verification methodologies and test bench development.

Key Responsibilities

Develop verification test plans
Build verification test benches
Assist FPGA emulation efforts
Collaborate with design engineers
Review design verification code and coverage

Technical Overview

Knowledge of SystemVerilog/UVM, SystemC, C/C++, object-oriented verification; will participate in test plan development, verification benches, and FPGA emulation efforts.

Ideal Candidate

The ideal candidate is an undergraduate student pursuing a degree in EE/CS with SystemVerilog/UVM experience, eager to learn ASIC verification and contribute to test benches and FPGA emulation in a fast-paced environment.

Must-Have Skills

Currently enrolled in a full-time undergraduate programKnowledge of SystemVerilog/UVMSystemCKnowledge of C and/or C++Knowledge of object-oriented verification methodologies

Nice-to-Have Skills

Knowledge of DSP algorithms and modulation techniques such as QAMLab silicon validation experienceKnowledge of Formal Verification methodologies and tools (e.g.Jasper)

Tools & Platforms

SystemVerilogUVMSystemCCC++

Required Skills

Currently enrolled in a full-time undergraduate programknowledge of SystemVerilog/UVMSystemCC/C++

Hard Skills

SystemVerilogUVMSystemCCC++Object-oriented verificationTest plansVerification test benchesFPGA emulation

Soft Skills

Fast learnerCollaborationCommunicationTeamwork

Industry & Role

Industry Technology

Job Function Support ASIC design verification efforts for next-generation optical products as an intern.

Role Subtype intern

Keywords for Your Resume

asic design verification internsystemveriloguvmsystemcc/c++test plansverification test benchesfpga emulationinternshipunited statesc++verificationtest benchesobject-oriented verificationundergraduate internshipc

Deal Breakers

Not enrolled as a full-time undergraduate student, Lack of SystemVerilog/UVM knowledge, Unwillingness to work on-site in the United States

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ASIC Design Verification Engineer I Intern - United States

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