Position Details
About this role
This role focuses on silicon debug, DFT, and yield engineering for advanced ASICs, utilizing data analysis, defect modeling, and industry tools to optimize manufacturing yield.
Key Responsibilities
- Debug silicon failures
- Implement DFT strategies
- Analyze yield data
- Collaborate with design and manufacturing teams
- Optimize yield processes
Technical Overview
The position involves ASIC design, physical design, yield analysis, big data processing, and defect management, with expertise in industry-standard yield tools and physical effects modeling.
Ideal Candidate
The ideal candidate is an experienced ASIC design engineer with 3+ years in Silicon Debug, DFT, or Yield Engineering, proficient in Python and SQL, with strong knowledge of industry yield management tools and physical effects in FinFET nodes.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 3 years experience in Silicon Debug or Yield Engineering, Lack of experience with industry yield management tools, No proficiency in Python or SQL
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