Position Details
About this role
This role involves leading DFT programs for advanced ASIC designs, focusing on test insertion, verification, and silicon debug to ensure high test coverage and yield.
Key Responsibilities
- Define DFT specifications
- Implement DFT features
- Generate and verify test vectors
- Debug silicon failures
- Collaborate with physical design
Technical Overview
The position requires expertise in ASIC design for testability, including scan insertion, ATPG, BIST, and verification using industry-standard tools and protocols, with collaboration across physical design and test teams.
Ideal Candidate
The ideal candidate is a mid-level ASIC DFT engineer with experience in scan insertion, ATPG, and silicon debug. They should have strong Verilog coding skills and familiarity with industry-standard DFT tools and protocols, capable of leading DFT programs from specification to verification.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of ASIC DFT experience, No Verilog coding skills, No experience with industry-standard DFT tools, Reluctance to work on physical design collaboration
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