Position Details

Salary $141K – $226K USD / year

Type Not Specified

Experience mid

Exp. Years 10+ years

Education Bachelor's and 12+ years of related experience; or Masters and 10+ years of related experience

Category Cybersecurity

About this role

This role involves leading DFT programs for ASIC designs, including scan insertion, ATPG, silicon debug, and yield improvement, primarily in a high-performance semiconductor environment.

Key Responsibilities

Leading DFT implementation
Pattern generation and verification
Silicon bring-up support
Debugging test vectors
Yield improvement initiatives

Technical Overview

Technical environment includes Verilog coding, ASIC design, physical design, industry standards IEEE1149.1 and IEEE1149.6, and automation of DFT flows for advanced process nodes.

Ideal Candidate

The ideal candidate is a senior ASIC DFT engineer with over 10 years of experience in scan insertion, ATPG, silicon debug, and physical design, proficient in Verilog and familiar with industry standards like IEEE1149.1 and IEEE1149.6.

Must-Have Skills

Verilog codingASIC DFTScan insertionATPGSilicon debugPhysical DesignTest vector generation

Nice-to-Have Skills

TetraMaxFastscanMemory BISTBoundary scanIEEE1149.1IEEE1149.6Test-STAIJTAGICLPDL

Tools & Platforms

Mentor TestKompressTetraMaxFastscanVerilog

Required Skills

ASIC DFTscan insertionATPGsilicon debugphysical designtest vectorsVerilogindustry standards

Hard Skills

VerilogASICDFTScanMBISTTAPLBISTIOSerDesATPGPattern generationVerificationSilicon debugYield improvementPhysical DesignSTAIEEE1149.1IEEE1149.6Test-STAIJTAGICLPDLCVerilog codingTestbench

Soft Skills

collaborationproblem-solvingcommunicationteamworkindependent judgment

Industry & Role

Industry Technology

Job Function Design and verification of testability features in ASIC chips

Role Subtype ASIC DFT Engineer

Tech Domains Verilog, ASIC, Physical Design, Test-STA, IEEE1149.1, IEEE1149.6, Boundary scan, Memory BIST

Keywords for Your Resume

ASIC DFTDesign for TestScan insertionATPGSilicon debugTest vectorsPhysical DesignTest-STAIEEE1149.1IEEE1149.6Boundary scanMemory BISTVerilogTestbenchSilicon bring-upYield improvementAutomating DFTTest Vector GenerationASICDFT Engineer

Deal Breakers

Lack of ASIC DFT experience, No Verilog coding skills, Less than 10 years of relevant experience

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