About this role
Drive ASIC/SoC DFT programs end-to-end, from chip-level DFT specification through implementation, verification, and successful product release to production. Own test insertion, pattern generation, coverage improvement, and post-silicon debug/yield improvement using ATE bring-up and diagnostics.
Key Responsibilities
- Lead chip level DFT specification through product release
- Implement DFT including scan, MBIST, TAP, LBIST, IO, SerDes integration
- Generate, verify, and debug test vectors for tape release and ATE bring-up
- Collaborate with STA and DI Engineers for DFT mode timing closure
- Support silicon failure analysis and yield improvement with customer/debug feedback
Technical Overview
Responsible for DFT architecture and implementation (Scan, MBIST, TAP, LBIST, IO, SerDes), including scan insertion/compression (DFT Compiler, Mentor TestKompress). Build and debug ATPG and BIST test vectors using Verilog-based workflows and tools like TetraMax and Fastscan, with boundary scan knowledge (IEEE1149.1/IEEE1149.6), embedded memory BIST (SRAM/CAM/eDRAM/ROM), and Test-STA/constraints.
Ideal Candidate
The ideal candidate is a senior ASIC DFT Engineer with 12+ years of experience (or 10+ with a Masters) driving chip-level SoC DFT programs from specification through release. They have deep expertise in scan insertion and scan compression (DFT Compiler and Mentor TestKompress), ATPG vector generation and debugging (TetraMax/Fastscan), and logic/memory BIST including embedded SRAM/CAM/eDRAM/ROM. Strong knowledge of IEEE1149.1 and IEEE1149.6 boundary scan and Test-STA/constraints is essential.
Must-Have Skills
chip level DFT specificationDFT architectureimplementing DFT including ScanMBISTTAPLBISTIOSerDes and other I/P DFT integrationpattern generation and verification at chip levelrapid bring-up at ATE and RMA supportvalidating and debugging test vectors before tape releasevalidating and debugging test vectors on ATE during the silicon bring up phasesilicon failure analysisdiagnosticsand yield improvement effortswork on SoC DFT related activitiesStrong DFT background (such as IO and Analog DFTATPG and/or ScanBISTand others)Scan Insertion and scan compression background (DFT CompilerMentor TestKompressetc.)Logic BIST design and debug experienceATPG vector generationsimulationand debugging (TetraMaxFastscan)IEEE1149.1 and IEEE1149.6 knowledgeBoundary scan verification and test vector generationVerilog codingtestbench generation and simulationMemory BIST insertion and verification experience on embedded (SRAMCAMeDRAMROM)Basic knowledge Test-STA and constraintsStrong background on IEE1687IJTAGICLand PDL
Nice-to-Have Skills
Automating DFT and test vector generation flowsInnovating newer DFT solutions to solve testability problems in 3nm and beyonddirect interaction with external customersworking with Physical Design and STA team for DFT mode timing closureworking globally with physical design and manufacturing teams
Tools & Platforms
DFT CompilerMentor TestKompressTetraMaxFastscanVerilogATE (Automatic Test Equipment)
Required Skills
DFT architectureDesign for testscan insertionscan compressionDFT CompilerMentor TestKompressMBISTTAPLBISTIOSerDespattern generationcoverage improvementpost silicon debugyield improvementATE (Automatic Test Equipment)RMA supporttest vectorsATPG (Automatic Test Pattern Generation)logic BISTTetraMaxFastscanVerilog codingtestbench generationsimulationmemory BIST insertion and verificationSRAMCAMeDRAMROMboundary scan verificationIEEE1149.1IEEE1149.6Test-STAconstraintsIEE1687IJTAGICLPDL
Hard Skills
Design for testDFT architecturescanscan insertionscan compressionDFT CompilerMentor TestKompressMBISTTAPLBISTIOSerDespattern generationATPG (Automatic Test Pattern Generation)test vector generationcoverage improvementpost silicon debugyield improvementATE (Automatic Test Equipment)RMA supportstatic timing analysisTest-STAconstraintssilicon failure analysisdiagnosticsIEEE1149.1IEEE1149.6I/P DFT engineersIEE1687IJTAGICLPDLVerilog codingtestbench generationsimulationTetraMaxFastscanMemory BIST insertion and verificationSRAMCAMeDRAMROMBoundary scan verificationBoundary scan test vector generationIEEE 1149.1IEEE 1149.6SoC DFT
Soft Skills
ability to work in a multi-disciplinedcross-department environmentinterfacing with the customercollaboration with STA and DI Engineersdebugging customer returned partsstrong communication skills (implied by interfacing globally)
Keywords for Your Resume
ASIC DFT EngineerDFTDesign for testSoC DFTDFT architecturechip level DFT specificationscanScan Insertionscan compressionDFT CompilerMentor TestKompressMBISTTAPLBISTIOSerDespattern generationcoverage improvementpost silicon debugyield improvementATEAutomatic Test EquipmentRMA supporttest vectorsATPGAutomatic Test Pattern Generationlogic BISTLogic BIST design and debugTetraMaxFastscanVerilogtestbench generationsimulationSRAMCAMeDRAMROMBoundary scan verificationIEEE1149.1IEEE1149.6Test-STAconstraintsIEE1687IJTAGICLPDLscan insertion
Deal Breakers
Must have 12+ years related experience with a Bachelors OR 10+ years with a Masters, Must have strong DFT background including scan/ATPG/BIST and scan insertion + scan compression, Must demonstrate knowledge of IEEE1149.1 and IEEE1149.6 boundary scan
Get matched to jobs like this
Luna finds roles that fit your skills and career goals — no endless scrolling required.
Create a Free Profile