✦ Luna Orbit — Software Engineering

ASIC Engineer Principal

at Hewlett Packard Enterprise

Hybrid Posted March 24, 2026
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Position Details

Type Not Specified
Experience senior
Exp. Years 7+ years
Education BS degree in electrical engineering, computer engineering, or related field
Category Software Engineering

About this role

This role involves leading physical design for large System-on-Chip (SoC) projects, from RTL to GDSII, ensuring timing, power, and manufacturing sign-off.

Key Responsibilities

  • Implement physical design
  • Interact with IP vendors
  • Build chip floorplan
  • Develop clock networks
  • Perform place and route

Technical Overview

The position requires extensive experience in ASIC physical design, IP integration, chip floorplanning, timing closure, and chip tapeout processes.

Ideal Candidate

The ideal candidate is a senior ASIC engineer with over 7 years of experience in physical design of large SoC chips, proficient in RTL to GDSII flow, IP integration, and chip tapeouts.

Must-Have Skills

7+ years experience in physical design of large SoC chipsExperience with RTL to GDSII flowIP integration and bump planning

Nice-to-Have Skills

Experience with chip tapeoutsKnowledge of formal verification

Tools & Platforms

RTLGDSIIPhysical Design ToolsStatic Timing AnalysisLVSDRCERCECODFT

Required Skills

ASICRTLGDSIIphysical designSoCIP integrationfloorplanstatic timingplace and routedesign verification

Hard Skills

ASICApplication Specific Integrated CircuitPhysical DesignRTLGDSIISoCBlock-level DesignTop-level DesignRTL to GDSIIIP IntegrationMicrobumpProbe BumpPad PlacementFloorplanPower GridRDL DesignStatic Timing ConstraintsPlace and RouteDesign VerificationLVSDRCERCECODFTTapeout

Soft Skills

CollaborationProblem-solvingAttention to detailTeamworkCommunication

Industry & Role

Industry Technology
Job Function ASIC physical design engineering for advanced SoCs
Role Subtype ASIC Engineer
Tech Domains ASIC, RTL, Physical Design, GDSII, SoC

Keywords for Your Resume

ASICApplication Specific Integrated CircuitPhysical DesignRTLGDSIISoCBlock-level DesignTop-level DesignRTL to GDSIIIP IntegrationMicrobumpProbe BumpPad PlacementFloorplanPower GridRDL DesignStatic Timing ConstraintsPlace and RouteDesign VerificationLVSDRCERCECODFTTapeoutStatic Timing

Deal Breakers

Less than 7 years experience in physical design, No experience with RTL to GDSII flow, Lack of IP integration or bump planning experience

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