Must-Have Skills
Proven background experiences in ASIC designKnowledge of AMBA AXI/AXI-S/APB interconnect protocolsExperienced with VerilogSystem VerilogSystemVerilog Assertions (SVA)Proficiency in writing and debugging SDC timing constraintsincluding multi-cycle pathsfalse pathsand clock domain crossing constraintsExperience in industry-standard ASIC CAD tools for simulationsynthesisSTALINTLECCDCRDC and power estimationetc.Experience in designs with multiple power domains and UPFProficiency with scripting languages like PerlPython and MakefileSystem level knowledge is a plus for supporting complex customer configuration issuesAcademic credentials: Bachelor's or Master's degree in Electrical Engineering or Computer Engineering
Nice-to-Have Skills
System level knowledge is a plus for customer configurationExperience with UPF and low-power design techniquesAdditional scripting languages
Tools & Platforms
VerilogSystemVerilogSystem Verilog Assertions (SVA)AMBA AXI/AXI-S/APBSDCUPFASIC CAD toolsSimulationSynthesisSTALINTLECCDCRDCPower estimation
Hard Skills
ASIC designVerilogSystem VerilogSystemVerilog Assertions (SVA)SDC timing constraintsUPF (power intent)AMBA AXI/AXI-S/APBMultiple power domainsclock domain crossingScripting (PerlPython and Makefile)Industry-standard ASIC CAD toolsSimulationSynthesisSTALINTLECCDCRDCPower estimation
Soft Skills
strong communicationcross-domain collaborationability to influence architecture decisionsteam orientation
Keywords for Your Resume
asic designverilogsystem verilogsystemverilog assertions svaamba axi/axi-s/apbsdc timing constraintsupfclock domain crossingpower domainssynthesissimulationstalintleccdcrdcpower estimationrtldesign for testVerilogSystemVerilogSystemVerilog Assertions (SVA)AMBA AXI/AXI-S/APBSDC timing constraintsUPFPython
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