✦ Luna Orbit — Software Engineering

ASIC Verification Engineer - Acacia (Hybrid)

at Cisco Systems

Hybrid 💰 $148K – $212K USD / year Posted March 28, 2026
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Position Details

Salary $148K – $212K USD / year
Type Not Specified
Experience mid
Exp. Years 6+ years
Education Bachelor's in Engineering or related field
Category Software Engineering

About this role

Lead verification of next-generation optical ASICs used in high-speed communication systems, ensuring design quality and coverage.

Key Responsibilities

  • Develop test plans
  • Create verification test benches
  • Apply verification techniques
  • Mentor verification team
  • Review verification coverage

Technical Overview

Involves ASIC design verification using SystemVerilog, UVM, and verification methodologies for optical communication ASICs.

Ideal Candidate

The ideal candidate is a senior ASIC verification engineer with extensive experience in SystemVerilog and UVM, capable of leading verification projects for high-speed optical ASICs in a hybrid work environment.

Must-Have Skills

ASIC verificationSystemVerilogUVMVerification methodologiesTest plan development

Nice-to-Have Skills

Coverage analysisVerification process improvementMentoring teammatesASIC design experience

Tools & Platforms

SystemVerilogUVM

Required Skills

ASICApplication-Specific Integrated CircuitsVerificationSystemVerilogUVMVerification MethodologiesTest PlansTest BenchesCoverage Metrics

Hard Skills

ASICApplication-Specific Integrated CircuitsVerificationSystemVerilogUVMVerification MethodologiesObject-Oriented VerificationTest PlansTest BenchesCoverage Metrics

Soft Skills

CommunicationCollaborationLeadershipMentoringProblem-solving

Industry & Role

Industry Telecom
Job Function ASIC verification engineering
Role Subtype SDET
Tech Domains Verilog, UVM, ASIC

Keywords for Your Resume

ASIC verificationSystemVerilogUVMverification methodologiestest planstest benchescoverage metricsASICverification engineersenior verificationhardware verificationASIC designverification processverification toolsverification techniques

Deal Breakers

Lack of ASIC verification experience, No SystemVerilog or UVM knowledge, Unwilling to work in Maynard, MA

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