Position Details
About this role
This role involves verifying high-speed communication ASICs, developing verification environments, and ensuring silicon success through comprehensive testing and validation.
Key Responsibilities
- Develop verification environments
- Verify silicon at block and chip levels
- Automate verification workflows
- Collaborate with architecture and design teams
- Ensure first-pass silicon success
Technical Overview
The technical environment includes HDL languages (SystemVerilog, Verilog, VHDL), UVM methodology, scripting in Python, Perl, TCL, and ASIC design verification for high-performance PHYs.
Ideal Candidate
The ideal candidate is a mid-level ASIC verification engineer with 3+ years of experience in verification using SystemVerilog, Verilog, or VHDL, and familiar with IEEE Ethernet protocols and UVM methodology. They are proactive, detail-oriented, and capable of developing verification environments for high-speed communication ASICs.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of experience with HDL languages, No ASIC verification background, Inability to work with IEEE Ethernet protocols, No scripting experience in Python, Perl, or TCL
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