Position Details
About this role
This role involves verifying high-speed ASIC designs, developing verification environments, and ensuring protocol compliance for next-generation interconnect products.
Key Responsibilities
- Verify ASIC silicon designs
- Develop verification testbenches
- Ensure protocol compliance
- Collaborate with design teams
- Automate verification workflows
Technical Overview
The environment includes SystemVerilog, UVM, C, Python, and scripting tools, focusing on ASIC verification and protocol analysis.
Ideal Candidate
The ideal candidate is a mid-level ASIC verification engineer with experience in SystemVerilog, UVM, and scripting languages, capable of developing verification environments for high-speed interconnect products.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Clearance & Visa
Keywords for Your Resume
Deal Breakers
Less than 3 years ASIC verification experience, No experience with SystemVerilog or UVM, Lack of scripting skills, Inability to work independently
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