Position Details

Type Not Specified

Experience senior

Exp. Years 7-12 years preferred

Education BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Category QA & Testing

About this role

The Infinity Fabric Verification Engineer role focuses on verifying AMD's Infinity Fabric interconnects and AI accelerators through SystemVerilog/UVM-based DV environments.

Key Responsibilities

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects
Develop and enhance BFM/UVC for industry-wide and AMD internal protocols
Collaborate with architects, hardware engineers and multiple IP development groups
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in Infinity Fabric architecture
Mentor junior engineers

Technical Overview

Hands-on verification for complex IP blocks, including testbenches, UVM, Verilog/C++, and emulation; collaboration with RTL and architecture teams; familiarity with AI DV.

Ideal Candidate

The ideal candidate is a senior verification engineer with deep SystemVerilog/UVM experience, capable of building DV environments for Infinity Fabric IP across server/data center products, and mentoring junior engineers.

Must-Have Skills

Expert in complex IP level verification; strong understanding CPU or Fabric micro-architectureCache coherencyscalable fabric / IO architecture is mandatoryDriving DV innovationefficiency and quality initiativesworking closely with RTL and architects for for improving product quality is mandatory and primary part of the roleProficient in using UVM testbenches; Good understanding and hands-on experience in the UVM concepts and System VerilogExperienced with VerilogSystem VerilogCand C++; PerlRubyExperienced with working on complex server / data centre products is strongly preferredExperience on AI / ML acceleratorsdata center GPUs will be an added advantageExpertise in formal verification and ability to use AI tools for productivity and DV innovation would be added advantage

Nice-to-Have Skills

Experience with AI accelerators or data center GPUsExposure to formal verification and AI tools for productivity

Tools & Platforms

SystemVerilogUVMVerilogC++PerlRubyMake

Required Skills

SystemVerilogUVMtestbenchesVerilogC++RTL designPerlRubyformal verificationemulationInfinity Fabric

Hard Skills

SystemVerilogUVMtestbenchesBFMUVCVerilogC++PerlRubyRTL designformal verification

Soft Skills

mentoringteam collaborationcommunicationproblem-solving

Industry & Role

Industry Technology

Job Function Verify Infinity Fabric interconnects by building robust DV environments and leading DV initiatives across multiple teams

Role Subtype Senior verification engineer

Tech Domains SystemVerilog, UVM, Verilog, C++, Perl, Ruby, Formal verification, Emulation

Keywords for Your Resume

data fabric verification architectinfinity fabricsystemveriloguvmtestbenchesbfmuvcverilogc++perlrubyformal verificationemulationrtl designcpu micro-architecturefabric micro-architectureserverdata centerai toolsinfinity fabric architecturebfm/uvc

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Data Fabric Verification Architect

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