✦ Luna Orbit — Software Engineering

Density Fill PDK Development Engineer

at Intel

📍 4 Locations Hybrid 💰 $111K – $211K USD / year Posted April 02, 2026
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Position Details

Salary $111K – $211K USD / year
Type Full-Time
Experience senior
Exp. Years 6+ years (Bachelor's) or 3+ years (Master's) or 3+ years (PhD)
Education Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of relevant experience OR Master's degree with 3+ years of relevant experience
Category Software Engineering

About this role

Senior density fill development engineer to advance PDK density fill capabilities and EDA tooling within Intel Foundry, enabling manufacturability at advanced nodes.

Key Responsibilities

  • Design, develop, and debug Fill components of Process Design Kits (PDKs)
  • Provide algorithmic solutions using Calibre, ICV, and Pegasus
  • Collaborate with process developers and end users to define requirements
  • Automate workflows across design teams
  • Maintain documentation and user guides

Technical Overview

Focus on density fill, PDk development, EDA tooling (Calibre/ICV/Pegasus), and advanced physical design rules with Unix/Linux environments.

Ideal Candidate

The ideal candidate is a senior density fill development engineer with deep expertise in EDA tools and PDKs, capable of delivering advanced fill solutions within Intel Foundry constraints.

Must-Have Skills

Bachelor's degree in Electrical EngineeringComputer Engineeringor a related field with 6+ years of relevant experience OR Master's degree with 3+ years of relevant experienceProficiency in scripting languages such as PythonTclor Perl for automationExpertise in EDA toolsincluding CalibreICVor Pegasuswith strong skills in developing and debugging rule decks (e.g.SVRF/TVFPXLPVL/PVTCL)Solid understanding of semiconductor device physicsprocess technologyand design rulesExperience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodesStrong knowledge of Unix/Linux platforms and computing environments

Nice-to-Have Skills

Experience with advanced physical verification techniquesincluding DRCand density/fill modulesFamiliarity with Cadence Virtuoso or Synopsys Custom DesignerDeep understanding of technology scaling challenges and their impact on physical design rules

Tools & Platforms

CalibreICVPegasusCadence VirtuosoSynopsys Custom Designer

Required Skills

PythonTclPerlCalibreICVPegasusSVRF/TVFPXLPVL/PVTCLUnixLinuxDRCdensity/fillCadence VirtuosoSynopsys Custom Designeralgorithmic solutions

Hard Skills

PythonTclPerlCalibreICVPegasusSVRF/TVFPXLPVL/PVTCLUnixLinuxDRCdensity/fillCadence VirtuosoSynopsys Custom Designeralgorithmic solutionsEDA tools

Soft Skills

communicationanalytical thinkingproblem solvingleadershipteam collaboration

Certifications

Preferred

PhD in Computer ScienceElectrical Engineering & Computer ScienceElectrical & Computer Engineeringor related computing discipline

Industry & Role

Industry Manufacturing
Job Function ed a tooling engineer enabling density fill and pdk modernization
Role Subtype eda tooling engineer
Tech Domains Linux, Python

Keywords for Your Resume

density fillpdksprocess design kitspdkcalibreicvpegasussvrf/tvfpxlpvl/pvtclcadence virtuososynopsys custom designerlinuxunixdrcdensity/fillsemiconductor device physicsprocess technologydesign rulespythontclperlalgorithmic solutionseda tools

Deal Breakers

Bachelor's degree with 6+ years or higher, Experience with Calibre/ICV/Pegasus, Strong Unix/Linux background

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