Position Details

Salary $95K – $176K USD / year

Type Full-Time

Experience senior

Exp. Years 5-7 years

Education 4 year degree; or 3 years and an advanced degree; or equivalent work experience.

Category Engineering (Non-Software)

About this role

Design Verification Engineer will execute complete verification projects as a senior engineer, including mentoring and client communications. The role focuses on building UVM-based SystemVerilog testbenches, defining block/sub-system/SOC top-level test plans, and applying verification flows and quality metrics across key subsystems.

Key Responsibilities

Execute complete verification project as senior engineer with hands-on experience
Provide guidance on developing UVM-based SV test-benches
Define block, sub-system and SOC top level test plans
Drive verification methodologies, flows and quality metrics for PCIe, NVMe, NAND, DDR, and CPU sub-systems
Conduct in-depth technical reviews and mentor team members

Technical Overview

Hands-on verification engineering centered on UVM-based SV test-benches and comprehensive verification planning for SOC and sub-systems. The scope includes PCIe, NVMe, NAND, DDR, and CPU subsystem verification using defined methodologies, flows, and quality metrics.

Ideal Candidate

The ideal candidate is a senior design verification engineer with 5-7 years of related experience and a strong background executing end-to-end verification projects. They have hands-on expertise building UVM-based SystemVerilog (SV) test-benches and defining SOC top level and sub-system verification plans across PCIe, NVMe, NAND, DDR, and CPU sub-systems.

Must-Have Skills

UVM-based SV test-benchesdefining blocksub-system and SOC top level test plansPCIeNVMeNANDDDRCPU sub-systemsverification methodologiesverification flowsquality metricsExecute complete verification project

Tools & Platforms

UVM

Required Skills

verification project executionUVM-based SV test-benchesUVMSystemVerilog (SV)block test planssub-system test plansSOC top level test plansPCIeNVMeNANDDDRCPU sub-systemsverification methodologiesverification flowsquality metricstechnical reviewsclient communicationmentoring

Hard Skills

verification project executionUVM-based SV test-benchesUVMSystemVerilog (SV)defining block test plansdefining sub-system test plansSOC top level test plansPCIe verificationNVMe verificationNAND verificationDDR verificationCPU sub-systems verificationverification methodologiesverification flowsquality metricstechnical reviewsclient communicationtechnical mentoring

Soft Skills

mentoringclient communicationinteractionsin-depth technical reviews participationindependent problem-solvingresource for colleaguesinformal guidance to junior staffprocess improvement contributionminimal guidance executionteam guidance

Industry & Role

Industry Manufacturing

Job Function Lead end-to-end design verification planning and execution for complex SOC subsystem architectures

Role Subtype QA Lead

Keywords for Your Resume

Design Verification Engineerverification projectUVM-based SV test-benchesUVMSystemVerilogtest-benchesSOC top level test plansblock test planssub-system test plansPCIeNVMeNANDDDRCPU sub-systemsverification methodologiesverification flowsquality metricstechnical reviewsclient communicationmentoring

Deal Breakers

UVM-based SV test-benches experience required, Must have experience defining SOC top level test plans and verification methodologies, Must have PCIe, NVMe, NAND, DDR, and CPU sub-systems verification experience

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