Position Details
About this role
This role involves designing and optimizing hardware test architectures for custom System on Chips (SoCs) used in AWS Machine Learning servers, focusing on high-quality test coverage and silicon debug.
Key Responsibilities
- Define DFT architectures
- Implement DFT solutions with physical design teams
- Perform RTL coding and verification
- Utilize industry standard DFT tools
- Participate in silicon debug efforts
Technical Overview
The position requires expertise in ASIC design, RTL coding in Verilog/SystemVerilog, industry standard DFT tools, silicon debug, and working with advanced technology nodes for high-performance hardware.
Ideal Candidate
The ideal candidate is a mid-level ASIC DFT Design Engineer with 5+ years of experience in designing and optimizing test architectures for advanced technology nodes, proficient in RTL coding, verification, and silicon debug, with strong scripting skills.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 5 years of DFT experience, Lack of experience with industry standard DFT tools, No experience with silicon debug or yield optimization, Bachelor's degree only, no advanced degree preferred
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