About this role
Design digital signal processing blocks for next-generation optical data center connectivity products and validate the ASIC architecture both pre- and post-silicon. The role focuses on translating high-level CDR and equalization concepts into synthesizable Verilog and using simulation and DFT practices to hit performance, power, and cost metrics.
Key Responsibilities
- Design digital signal processing blocks for optical data center connectivity
- Validate ASIC architecture post and pre-silicon
- Translate CDR and equalization architectures into Verilog for logic synthesis
- Use Matlab/Simulink and Verilog-HDL/System Verilog for coding and simulation
- Apply DFT, scan, synthesis, CDC, static timing analysis, and SDF annotated simulations
Technical Overview
Work on SerDes and high-speed optical/electrical interconnect architectures (100G/200G/400G per lane PAM4 and NRZ), including ADC-based design trade-offs. Use Matlab/Simulink and Verilog-HDL/System Verilog to implement and validate DSP blocks, supported by NCVerilog/NCSIM/Simvision/Spyglass and SDF annotated simulations, while applying DFT (scan/DFT-friendly RTL), CDC, synthesis, and static timing analysis.
Ideal Candidate
The ideal candidate is an experienced digital signal processing engineer with 6+ years (or a PhD with 3+ years) working on SerDes and high-speed data center networking. They have strong post-silicon validation experience for digital and analog mixed-signal IPs, and they can translate CDR and equalization architectures into Verilog for logic synthesis. Proficiency with Matlab/Simulink, Verilog-HDL/System Verilog, and validation toolchains like NCVerilog/NCSIM is essential.
Must-Have Skills
digital signal processing design for SerDes (Serializer-Deserializer)post silicon validation of digital and analog mixed-signal IPsADC (Analog-to-Digital Converter) and analog based optical and electrical interconnect architectures such as 100G/200G/400G per lane PAM4 and NRZ design trade-offstranslating CDR (Clock and Data Recovery) and equalization architectures into Verilog code for logic synthesisMatlabSimulinkVerilog-HDLSystem Verilog codingfront end tools such as NCVerilogNCSIMSimvisionSpyglassDesign for testscan conceptwriting DFT friendly RTLsynthesisCDCstatic timing analysisSDF annotated simulations
Nice-to-Have Skills
high speed DSP applications and algorithmshigh speed ADCFFEDFECDR Adaptation algorithms for PAM4 signalslogic optimization for low powertiming margins & DFTSignal Integrity and Power Integrity modeling for High Speed designsVerilog AMS simulationbehavioral models of analog circuitsmultifunctional role
Tools & Platforms
MatlabSimulinkVerilog-HDLSystem VerilogNCVerilogNCSIMSimvisionSpyglass
Required Skills
digital signal processingSerDes (Serializer-Deserializer)post silicon validationdigital and analog mixed-signal IPsADC (Analog-to-Digital Converter)PAM4NRZCDR (Clock and Data Recovery)equalizationVeriloglogic synthesisMatlabSimulinkVerilog-HDLSystem VerilogNCVerilogNCSIMSimvisionSpyglassDesign for testscan conceptDFT friendly RTLsynthesisCDCstatic timing analysisSDF annotated simulationsparasitic delays
Hard Skills
digital signal processingdigital signal processing designSerDes (Serializer-Deserializer)serial link high-speed data center networkingpost silicon validationdigital and analog mixed-signal IPsADC (Analog-to-Digital Converter)PAM4 (Pulse Amplitude Modulation 4)NRZ (Non-Return-to-Zero)CDR (Clock and Data Recovery)equalizationVeriloglogic synthesisMatlabSimulinkVerilog-HDLSystem VerilogNCVerilogNCSIMSimvisionSpyglassDesign for testscan conceptDFT friendly RTLsynthesisCDCstatic timing analysisSDF annotated simulationsparasitic delays
Soft Skills
strong written and verbal communication skillsability to speak to various technical and management levelsproactive approach to innovationcollaborative approachcreative approach to innovationconsensus facilitation to influence optimal project resultsexcellent time and task managementinterpersonal skills
Keywords for Your Resume
Digital Signal Processing and System Validation Engineerdigital signal processingSerDesSerializer-Deserializerpost silicon validationdigital and analog mixed-signal IPsADCAnalog-to-Digital Converter100G200G400GPAM4Pulse Amplitude Modulation 4NRZNon-Return-to-ZeroCDRClock and Data RecoveryequalizationVeriloglogic synthesisMatlabSimulinkVerilog-HDLSystem VerilogNCVerilogNCSIMSimvisionSpyglassDesign for testDFT friendly RTLscan conceptsynthesisstatic timing analysis
Deal Breakers
Must have MS in Electrical Engineering or Computer Engineering with 6+ years experience OR PhD with 3+ years experience in digital signal processing design for SerDes, Must demonstrate post silicon validation experience for digital and analog mixed-signal IPs, Must have hands-on Verilog (including System Verilog) and Matlab/Simulink experience
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