About this role
AMD is seeking an FPGA Prototyping and Emulation Engineer to build FPGA prototypes that validate IP/SoC functionality and support both pre-si and post-silicon validation. The role also involves improving the prototyping environment for faster runtime and better debugging, with cross-team collaboration across RTL, DV, Emulation, Firmware, and Silicon Bringup.
Key Responsibilities
- Create FPGA prototyping builds to validate IP/SoC functionality
- Collaborate with design, verification and validation teams to debug pre-si issues and support post-silicon validation
- Maintain and improve the hardware prototyping environment for runtime performance and debug facility
- Perform technical debug across FPGA, RTL, and test environments
- Provide technical support to other teams
Technical Overview
You will create and maintain FPGA prototyping builds and environments, debug issues discovered during pre-si validation, and support post-silicon validation. The work spans RTL development in SystemVerilog/Verilog, synthesis/place-and-route/timing closure, infrastructure scripting and flows, and integration of custom transactors and high-speed interfaces. Experience with SoC buses/protocols such as AXI, ACE, APB, PCIe, DDR, Ethernet, and SerDesbased links is strongly aligned.
Ideal Candidate
The ideal candidate is an FPGA prototyping and emulation engineer with strong hands-on experience creating FPGA prototyping builds to validate IP/SoC functionality. They are comfortable debugging across pre-si validation and supporting post-silicon validation, with a strong RTL background in SystemVerilog/Verilog and experience with FPGA build flows, timing closure, and SoC bus protocols.
Must-Have Skills
Create FPGA prototyping builds to validate the IP/SoC functionalityCollaborate with designverification and validation teams to debug issues found during pre-si validationSupport post-silicon validationMaintain and improve current hardware prototyping environment to speed up the runtime performance and improve the debug facilityProvide technical support to other teamsStrong RTL design background using SystemVerilog/Verilog
Nice-to-Have Skills
Strong experience in FPGA prototypingPartition large SoC RTL for multiFPGA platformsPerform synthesisplaceandroutetiming closureand resource optimization for FPGA buildsDevelop and maintain FPGA build infrastructure including scriptsflowsand makefilesIntegrate custom transactorshighspeed interfacesand debug instrumentationValidate system functionality by running architectural testsdiagnosticsdirected testsand firmwareDrive debug of functionaltimingor toolrelated issues across FPGARTLand test environmentsWork across teams (RTLDVEmulationFirmwareSilicon Bringup) to rootcause and resolve issues efficientlyHandson experience with Synopsys HAPSProtiumPalladiumor other FPGA/emulation platformsExperience with SoC buses and protocols: AXIACEAPBPCIeDDREthernetSerDesbased linksetc.
Tools & Platforms
Synopsys HAPSProtiumPalladiumFPGA/emulation platformsmakefilesSystemVerilogVerilog
Required Skills
FPGA prototypingemulationdesign verificationpre-si validationpost-silicon validationhardware prototyping environmentruntime performancedebug facilitySystemVerilogVerilogmultiFPGAsynthesisplaceandroutetiming closureresource optimizationFPGA build infrastructurescriptsflowsmakefilescustom transactorshighspeed interfacesdebug instrumentationarchitectural testsdiagnosticsdirected testsfirmwareSynopsys HAPSProtiumPalladiumAXIACEAPBPCIeDDREthernetSerDesbased links
Hard Skills
design verificationFPGA prototypingFPGA prototyping buildsvalidate IP/SoC functionalitydebug issues during pre-si validationpost-silicon validation supportmaintain and improve hardware prototyping environmentruntime performancedebug facilitymoderncomplex processor architecturedigital designverificationarchitectural testsdiagnosticsdirected testsfirmware validationdebug of functional issuesdebug of timing issuesdebug of toolrelated issuesrootcause and resolve issues across FPGARTLand test environmentspartition large SoC RTL for multiFPGA platformssynthesisplaceandroutetiming closureresource optimization for FPGA buildsdevelop and maintain FPGA build infrastructurescriptsflowsmakefilesintegrate custom transactorshighspeed interfacesdebug instrumentationStrong RTL design background using SystemVerilog/VerilogSystemVerilogVerilogSoC buses and protocolsAXIACEAPBPCIeDDREthernetSerDesbased linksSynopsys HAPSProtiumPalladiumFPGA/emulation platformsEmulation
Soft Skills
adaptiveself-motivativeteam playerexcellent communication skillscollaboration with other engineers located in different sites/time zonesstrong analytical and problem-solving skillswillingness to learnready to take on problemstechnical support to other teams
Keywords for Your Resume
FPGA Prototyping and Emulation EngineerFPGA prototyping buildsvalidate the IP/SoC functionalitypre-si validationpost-silicon validationhardware prototyping environmentruntime performancedebug facilitySystemVerilogVerilogpartition large SoC RTL for multiFPGA platformssynthesisplaceandroutetiming closureresource optimizationFPGA build infrastructurescriptsflowsmakefilescustom transactorshighspeed interfacesdebug instrumentationarchitectural testsdiagnosticsdirected testsfirmwareSynopsys HAPSProtiumPalladiumAXIACEAPBPCIeDDREthernetSerDesbased links
Deal Breakers
Must be able to create FPGA prototyping builds to validate IP/SoC functionality, Must have strong RTL background using SystemVerilog/Verilog, Must be able to debug issues found during pre-si validation and support post-silicon validation
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