Position Details

Type Not Specified

Experience mid

Exp. Years Not specified

Education Undergrad degree required. Masters degree or related in computer engineering/Electrical Engineering is preferred.

Category QA & Testing

About this role

Plan, build, and execute verification of AMD graphics processor IP, aiming for the final design to be bug-free. Collaborate with architects, hardware, firmware, and software teams to develop tests and ensure adequate coverage.

Key Responsibilities

Collaborate with architects, hardware engineers, and firmware engineers to understand features to be verified
Build test plan documentation considering interactions with hardware, firmware, and software driver use cases
Estimate time to write new feature tests and test-environment changes
Build directed and random verification tests
Debug test failures and resolve design defects with RTL/firmware teams

Technical Overview

Scope includes IP-level ASIC verification using Verilog/SystemVerilog with UVM testbenches on Linux/Windows. Familiarity with testbenches, RTL debugging, and C/C++ is required; SystemC and TLM experience is a plus.

Ideal Candidate

The ideal candidate is an ASIC verification engineer with GPU IP experience, proficient in Verilog/SystemVerilog, UVM, C/C++, and testbenches; comfortable working across Linux/Windows and collaborating with RTL, firmware, and hardware teams.

Must-Have Skills

Undergrad degree requiredIP level ASIC verificationVerilog/SystemVerilogUVM testbenchesCC++LinuxWindows

Nice-to-Have Skills

UVM based verification frameworksLinux/Windows experienceAutomating workflows in distributed compute environmentExposure to HLS tools/processC++ on Linux with exposure to WindowsSystemCTLMVideo codec systemsMultimedia solutionsLeadership or mentorship

Tools & Platforms

VerilogSystemVerilogUVMLinuxWindowsSystemCTLM

Required Skills

VerilogSystemVerilogUVMtestbenchesASIC verificationVerilogSystemVerilogCC++LinuxWindowsSystemCTLMPerlRubyMakefileshell

Hard Skills

VerilogSystemVerilogCC++UVMtestbenchesLinuxWindowsSystemCTLMPerlRubyMakefileshellHLS tools/processASIC verification

Soft Skills

strong communicationteam playercollaborationproblem-solvinganalytical thinkinglearning orientation

Industry & Role

Industry Manufacturing

Job Function Plan, develop, and execute verification of GPU IP to ensure a bug-free final design

Role Subtype SDET

Tech Domains Verilog, SystemVerilog, Linux, Windows, UVM, SystemC, TLM, C++, C, GPU IP

Clearance & Visa

Visa Sponsorship No

Keywords for Your Resume

GPUDesign VerificationASIC verificationIP level ASIC verificationUVMSystemVerilogVerilogCC++LinuxWindowsSystemCTLMPerlRubyMakefileshellHLS tools/processtestbenchesgraphics pipelinevideo codecmultimediadebuggingRTLfirmwarecollaborationGPU IP

Deal Breakers

Not eligible for visa sponsorship

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GPU Design Verification Engineer

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