Position Details

Salary $148K – $212K USD / year

Type Not Specified

Experience senior

Exp. Years 5+ years

Education Bachelor's degree in Electrical Engineering or related field

Category Engineering (Non-Software)

About this role

Senior FPGA design role focused on designing and verifying FPGAs for Acacia's optical transceiver product and evaluation platform. The position combines hardware design with software automation and ASIC RTL collaboration in a hybrid Cisco environment.

Key Responsibilities

Design/Verify FPGAs for Acacia's product and evaluation platform
Write Python routines for Test Development and Automation
Contribute to FPGA Emulation of ASIC Blocks
Contribute to custom ASIC RTL code
Collaborate with Hardware, Software, Optics, and manufacturing teams

Technical Overview

Hands-on FPGA design and verification using Verilog RTL; Xilinx toolchains (ISE, Vivado) with FPGA emulation and ASIC RTL integration. Requires experience with SPI/I2C/MDIO interfaces, high-speed SERDES, Python automation, and Linux.

Ideal Candidate

The ideal candidate is a senior FPGA design engineer with 5+ years of FPGA design and verification experience, strong Verilog RTL skills, and hands-on experience with Xilinx toolchains (ISE and Vivado). The role requires collaboration across hardware, software, optics, and manufacturing teams in a hybrid office environment in Maynard, MA.

Must-Have Skills

5+ years of FPGA design and verification experienceExperience in Verilog RTL coding and synthesis for FPGAsExperience with Python and LinuxExperience designing interfaces with ProcessorsSPI & I2C devicesMDIOhigh speed SERDESExperience in Xilinx design tool chain (ISE/Vivado)

Nice-to-Have Skills

C/C++embedded MCUsmulti-clock-domain timing closurelab/test equipment bring-upAnalog components (OpAmpsDACs/ADCs)

Tools & Platforms

Xilinx ISEVivadoSynopsys VCSSynplify

Required Skills

Verilog RTLFPGA designFPGA verificationPythonLinuxSPII2CMDIOhigh speed SERDESXilinx ISEVivadoXilinx Ultrascale+ASIC RTL codeFPGA emulationTest Development and AutomationOpAmpsDACs/ADCsclock domains

Hard Skills

Verilog RTLFPGAsXilinx ISEVivadoPythonLinuxSPII2CMDIOhigh speed SERDESASIC RTL codeFPGA EmulationTest Development and AutomationXilinx(R)ISE(R)Vivado(R)Synopsys VCSSynplify(R)ASIC RTL

Soft Skills

team collaborationproblem-solvingself-drivencommunication

Industry & Role

Industry Manufacturing

Job Function Design and verify FPGA-based hardware for Acacia product platforms

Role Subtype FPGA Engineer

Tech Domains Python, Linux

Keywords for Your Resume

Verilog RTLFPGAsPythonLinuxSPII2CMDIOhigh speed SERDESXilinx(R) design tool chainISE(R)Vivado(R)Xilinx ISESynopsys VCSSynplify(R)ASIC RTL codeFPGA EmulationTest Development and AutomationUltrascale+OpAmpsDACs/ADCsclock domainsFPGAVivado

Deal Breakers

Less than 5 years FPGA design/verification experience, No Verilog RTL or Xilinx Vivado/ISE experience, No experience with high-speed SERDES or SPI/I2C/MDIO, Lack of lab/test equipment experience

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Hardware FPGA Design Engineer - Acacia (Hybrid)

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