Position Details
About this role
This role involves leveraging AI/ML techniques to improve silicon yield, perform advanced silicon debug, and analyze manufacturing data for process optimization in semiconductor manufacturing.
Key Responsibilities
- Develop AI/ML models for defect classification
- Analyze yield data
- Collaborate across teams
- Implement defect binning
- Optimize manufacturing processes
Technical Overview
The position requires deep ASIC design knowledge, expertise in AI/ML applications, big data processing, and physical effects modeling, utilizing industry-standard tools and methodologies.
Ideal Candidate
The ideal candidate is a senior ASIC engineer with over 6 years of experience in silicon debug, DFT, and yield engineering, with expertise in AI/ML applications, proficient in Python and SQL, and familiar with industry yield management tools and physical effects in FinFET technology.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 6 years experience in Silicon Debug or Yield Engineering, Lack of AI/ML experience, No proficiency in Python or SQL
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