✦ Luna Orbit — AI & Machine Learning

IC Design AI/ML Silicon Debug & Yield Engineer

at VMware

📍 2 Locations Unknown 💰 $108K – $192K USD / year Posted March 13, 2026
Salary $108K – $192K USD / year
Type Not Specified
Experience mid
Exp. Years 3+ years
Education Bachelor's degree plus 8+ years or Master's plus 6+ years
Category AI & Machine Learning

This role involves developing AI/ML models to analyze silicon failure data, predict yield issues, and improve manufacturing processes for advanced semiconductor devices.

  • Develop ML models for failure classification
  • Analyze failure data
  • Collaborate with manufacturing teams
  • Implement predictive yield models
  • Debug silicon failures

The position requires expertise in ASIC design, scan compression, BIST, ATPG, and applying machine learning techniques using Python, TensorFlow, and PyTorch to analyze large datasets and optimize yield.

The ideal candidate is an experienced silicon debug and yield engineer with strong expertise in AI/ML techniques applied to semiconductor manufacturing. They should have 6+ years of experience in ASIC design, data analysis, and developing predictive models to improve yield and diagnose failures.

ASIC DesignScan CompressionBISTATPGPythonML ModelsData AnalysisSilicon DebugYield Engineering
Deep Sub-micron (FinFET)Pattern RecognitionClusteringRegression ModelsBig Data Environments
PyTorchTensorFlowSparkSnowflakePDF SolutionsSynopsys YieldExplorerCadence Clarity
ASIC DesignScan CompressionBISTATPGPythonML ModelsData AnalysisSilicon DebugYield Engineering
PythonScikit-LearnPyTorchTensorFlowSQLBig DataSparkSnowflakeAI/MLData AnalysisYield ModelingSilicon DebugDFTPattern RecognitionClusteringRegression
analytical thinkingcross-functional collaborationproblem-solvingcommunicationleadership
Industry Semiconductor & Hardware
Job Function Silicon debug, yield analysis, and AI/ML application in semiconductor manufacturing
ASIC DesignScan CompressionBISTATPGPythonML ModelsData AnalysisSilicon DebugYield ModelingPattern RecognitionClusteringRegressionDeep Sub-micronFinFETBig DataSparkSnowflake

Less than 3 years in Silicon Debug or Yield Engineering, Lack of experience with AI/ML tools and techniques, No background in ASIC design or DFT, Inability to work with large data sets

Apply for this Position →

Get matched to jobs like this

Luna finds roles that fit your skills and career goals — no endless scrolling required.

Create a Free Profile