Position Details
About this role
This role involves leading advanced IC layout and physical design for high-performance semiconductor chips, ensuring timing closure and design rule compliance.
Key Responsibilities
- Design IC layouts
- Perform timing closure
- Resolve LVS/DRC/ERC errors
- Optimize cell architectures
- Collaborate with design teams
Technical Overview
The position requires expertise in physical implementation, semiconductor process nodes, verification errors, and EDA tools for IC design.
Ideal Candidate
The ideal candidate is a senior IC design engineer with over 7 years of experience in physical implementation, layout design, and semiconductor process technologies, capable of leading high-performance chip projects.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 7 years of experience in IC layout, Lack of experience with Place and Route tools, No background in semiconductor technologies, No experience with verification tools
Get matched to jobs like this
Luna finds roles that fit your skills and career goals — no endless scrolling required.
Create a Free Profile