Position Details

Type Not Specified

Experience senior

Exp. Years 7-12 years industry experience is preferred

Education BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Category QA & Testing

About this role

This role verifies the Infinity Fabric network-on-chip components, including configurable switches and die-to-die interconnects. The engineer will develop and enhance SystemVerilog/UVM testbenches and reusable verification components (BFM/UVC) to validate new features across multiple AMD markets.

Key Responsibilities

Develop and enhance SystemVerilog / UVM-based testbenches
Develop and enhance BFM/UVC for industry-wide and AMD internal protocols
Collaborate with architects and multiple IP development groups
Interact with RTL designers and post-silicon validation engineers to build Infinity Fabric expertise
Mentor junior engineers

Technical Overview

You will architect and execute verification using SystemVerilog and UVM, developing testbenches and BFM/UVC for both industry-wide and AMD internal protocols. Work includes deep collaboration with architects, RTL designers, performance engineers, and post-silicon validation, with optional strengths in C++ and scripting (Perl/Ruby/Make) and exposure to formal verification and RTL design.

Ideal Candidate

The ideal candidate is a senior verification engineer with proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog and UVM. They can build and enhance SystemVerilog/UVM testbenches, develop BFM/UVC for both industry-wide and AMD internal protocols, and collaborate closely with architects, RTL designers, and post-silicon validation teams in a metric-focused environment.

Must-Have Skills

Verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologiesCreating and executing on testplansDevelop and enhance SystemVerilog / UVM-based testbenchesDevelop and enhance BFM/UVC for industry-wide and AMD internal protocolsCollaborate with architectshardware engineers and multiple IP development groups

Nice-to-Have Skills

Architected and developed complex verification environments in SystemVerilog or C++ and infrastructurescripting using Perlscripting using RubyMakeRefactoring testbenchUVCor BFM code using Object-Oriented Programming (OOP) principlesExposure to RTL designsoftware developmentformal verification

Tools & Platforms

SystemVerilogUVM (Universal Verification Methodology)C++PerlRubyMake

Required Skills

Infinity Fabric verificationSystemVerilogUVMtestbenchestestplansBFMUVCC++PerlRubyMakeObject-Oriented Programming (OOP)protocolsIP level verificationSoC level verification

Hard Skills

Infinity Fabric verificationverifying complex design blocksIP level verificationSoC level verificationSystemVerilogUVM (Universal Verification Methodology)testplanstestbench developmentBFM/UVC developmentindustry-wide protocolsAMD internal protocolsBFD/UVC (UVC)architecting verification environmentsObject-Oriented Programming (OOP) principlesC++scripting using Perlscripting using RubyMakeformal verification exposureRTL design exposureMentoring junior engineers

Soft Skills

Excellent communication skillsPlanning skillsTeam playerComfortable collaborating with design and verification colleaguesMetric-focused environment mindsetMentorship

Industry & Role

Industry Semiconductors

Job Function Verify Infinity Fabric configurable switches and die-to-die interconnects using SystemVerilog/UVM.

Role Subtype Automation QA Engineer

Tech Domains QA & Testing

Clearance & Visa

Visa Sponsorship No

Keywords for Your Resume

Infinity Fabric Verification EngineerInfinity Fabricnetwork on the chipconfigurable switchesdie-to-die interconnectSystemVerilogUVMUniversal Verification MethodologytestbenchtestplansBFMUVCverification environmentsBFM/UVCindustry-wide protocolsAMD internal protocolsarchitectsRTL designerspost-silicon validation engineersperformance engineersC++Object-Oriented Programming (OOP)PerlRubyMakeformal verificationRTL designMentor junior engineers7-12 years industry experience is preferredvisa sponsorship

Deal Breakers

Must have SystemVerilog/UVM experience verifying complex design blocks at IP or SoC level, Must be able to develop and enhance SystemVerilog / UVM-based testbenches, Must be able to develop and enhance BFM/UVC for protocols

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