Position Details

Type Not Specified

Experience mid

Exp. Years 7-12 years

Education BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Category Engineering (Non-Software)

About this role

Infinity Fabric Verification Engineer at AMD verifies configurable switches and die-to-die interconnects, building SystemVerilog/UVM testbenches and BFM/UVC infrastructure across client, server, graphics, and semi-custom segments.

Key Responsibilities

Develop SystemVerilog/UVM-based testbenches
Develop and enhance BFM/UVC
Collaborate with architects, hardware engineers, and IP groups
Mentor junior engineers
Work with post-silicon validation teams

Technical Overview

Role emphasizes building verification environments with SystemVerilog/UVM, C++, and scripting; collaboration with RTL, arch, and validation teams; post-silicon validation experience is a plus.

Ideal Candidate

The ideal candidate is a senior hardware verification engineer with 7+ years of SystemVerilog/UVM experience, strong C++, RTL exposure, and scripting capability in Perl/Ruby; they should be able to architect and implement complex testbenches for Infinity Fabric interconnects.

Must-Have Skills

BS or MS in Electrical EngineeringComputer Engineeringor Computer Science7-12 years industry experienceSystemVerilog/UVM experiencetestbench/BFM/UVC experienceObject-Oriented programmingScripting (PerlRubyMake)

Nice-to-Have Skills

Experience in RTL designsoftware developmentformal verificationExperience communicating across teamsMentoring junior engineers

Tools & Platforms

SystemVerilogUVMC++PerlRubyMake

Required Skills

SystemVerilogUVMtestbenchesBFMUVCC++PerlRubyRTL exposurepost-silicon validation

Hard Skills

SystemVerilogUVMBFMUVCC++Object-Oriented ProgrammingPerlRubyRTL design exposurepost-silicon validationverification environmentstestbenches

Soft Skills

mentoringcollaborationcommunication

Industry & Role

Industry Technology

Job Function Verify Infinity Fabric interconnects through advanced verification environments and testbenches

Role Subtype Verification Engineer

Tech Domains SystemVerilog, UVM, C++, Perl, Ruby

Clearance & Visa

Visa Sponsorship No

Keywords for Your Resume

Infinity Fabric Verification Engineersystemveriloguvmverificationtestbenchesbfmuvcc++perlrubyrtlpost-silicon validationip verificationso c verificationarchitecture verificationhardware verificationrtl verification

Deal Breakers

Lack of SystemVerilog/UVM experience, Insufficient experience with testbenches or BFM/UVC, Inability to work in a hybrid Austin/Silicon Valley environment

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