✦ Luna Orbit — Engineering (Non-Software)

Untitled Position

at Company

Unknown Posted March 30, 2026
Type Full-Time
Experience entry
Exp. Years 0-2 years
Education Bachelor's or Master's degree in computer engineering/Electrical Engineering
Category Engineering (Non-Software)

DFT Verification Engineer role focused on verifying advanced DFT functions for a next-generation low power, high-performance microprocessor. Responsibilities include developing test benches and ensuring test coverage across RTL and gate-level designs.

  • Verify advanced DFT functions (BIST, JTAG/IEEE 1500)
  • Develop test benches and tests in Verilog/SystemVerilog/C++
  • Define and implement test plans and coverage
  • Write and maintain scripts
  • Collaborate with architecture and design teams

Hardware verification in digital design with emphasis on DFT methods, JTAG, BIST; coding in Verilog/SystemVerilog and C++ with scripting in Perl; interface with architects and circuit design teams.

Entry-level DFT verification engineer with 0-2 years of experience, strong Verilog/SystemVerilog skills, and familiarity with JTAG and test technologies. Eager to learn and collaborate with architectural teams on next-generation processors.

Bachelor's or Master's degree in computer engineering/Electrical Engineering with 0-2 years of experience
Project level experience with JTAG verificationExperience with VCSCadenceMentor GraphicsGood understanding of Computer Architecture and Logic Design
Design for TestDFTBISTJTAGIEEE 1500scan compressionpartitioned test structuresVerilogSystemVerilogC++Perltest benchesfunctional coverage
Design for Test (DFT)BISTJTAG/IEEE 1500scan compressionpartitioned test structuresVerilogSystemVerilogC++Perltest benchesfunctional coverage
communicationteam playerproblem solvingwillingness to learn
Industry Semiconductors
Job Function Design for Test verification on next-generation processor designs
Role Subtype Windows Sysadmin
Tech Domains Verilog, SystemVerilog, C++, Perl
DFT verification engineerdesign for testDFTBISTJTAGIEEE 1500scan compressionpartitioned test structuresVerilogSystemVerilogC++Perltest benchesfunctional coverageAMDAustin

Bachelor's degree not in EE/CE, Less than 0-2 years experience, Lack of Verilog/SystemVerilog experience

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