About this role
Staff Research Scientist to architect AI-Hardware Co-Design; bridge AI algorithms and hardware; lead co-design from architecture to proof-of-concept; mentor engineers.
Key Responsibilities
- Strategic problem definition and architecture; research-to-product; feasibility analysis; system-level co-design; mentorship and thought leadership
Technical Overview
Seeks expertise in AI hardware co-design, edge AI, RTL, and cycle-accurate simulation; experience with PyTorch/JAX for model optimization; tape-out heavy background.
Ideal Candidate
The ideal candidate is a senior CPU/GPU/AI hardware architect or researcher with a PhD and a track record of silicon tapeouts and publications, proficient in RTL and model-optimization for edge AI.
Must-Have Skills
PhD specialized in Computer Architecture or Integrated Circuit Design for AI workloads3+ years of industry experience applying architectural principles to real-world engineering constraintsProven Silicon Execution: taped out a complex SoC or AI acceleratorHands-on RTL experience with Verilog/SystemVerilog or ChiselStrong publication record in top conferences/journals
Nice-to-Have Skills
Familiarity with Verilog/SystemVerilog or Chisel (beyond daily usage)Experience with PyTorch/JAX for training/fine-tuning models to validate architectural hypothesesKnowledge of memory hierarchy optimization and dataflow tilingExperience with FP32/INT8 mixed-precision quantizationEdge AI compute frameworks
Required Skills
PhD in Computer Architecture or IC Design; 3+ years industry experience; tape-out experience; RTL (Verilog/SystemVerilog or Chisel); PyTorch/JAX; edge AI; cycle-accurate simulation; publication record
Hard Skills
PythonPyTorchJAXINT8memory hierarchyon-chip networkscycle-accurate simulationChiselVerilogSystemVerilogDSPedge AIAI hardware co-designRTLhardware-software co-design
Soft Skills
leadershipmentoringcommunicationteamworkproblem-solvingcreative thinkingdecision-making
Keywords for Your Resume
Staff Research ScientistAI-Hardware Co-DesignPyTorchJAXINT8VerilogSystemVerilogChiselPythonEdge AIAI acceleratorRTLDSPMemory hierarchyOn-chip networkscycle-accurate simulation
Deal Breakers
PhD not in AI hardware or architecture? not applicable, Lack of tape-out experience, No publication record, No RTL experience
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