✦ Luna Orbit — Engineering (Non-Software)

Untitled Position

at Company

Hybrid Posted March 30, 2026
Type Not Specified
Experience senior
Exp. Years 5+ years
Education Bachelor's degree in Electrical Engineering or related field
Category Engineering (Non-Software)

FPGA design engineer responsible for design/verification of FPGA blocks for Acacia product line, including Verilog RTL coding, Python-based test development, and Xilinx tool flow.

  • Design/Verify FPGAs
  • Write Python tests
  • FPGA emulation
  • Contribute to RTL code
  • Collaborate with cross-functional teams

FPGA-centric hardware design with Xilinx toolchain (ISE, Vivado), Verilog RTL, high-speed interfaces, and lab bring-up; Python and Linux for test and automation.

A high-energy FPGA design engineer with 5+ years of FPGA design/verification experience, strong Verilog RTL skills, and hands-on experience with Xilinx tools and high-speed interfaces for Acacia products.

5+ years of FPGA design and verification experienceExperience with Verilog RTL coding and synthesis for FPGAsExperience with Python and LinuxExperience designing interfaces with ProcessorsSPI & I2C devicesMDIOhigh speed SERDESExperience in Xilinx design tool chain (ISEVivado)
C/C++embedded MCUsmulti-clock domain timing closurelab/test equipmentanalog components (OpAmpsDACs/ADCs)
FPGA designVerilog RTLXilinx ISEVivadoPythonLinuxSPII2CMDIOSERDESUltrascale+
Verilog RTL codingXilinx design tool chain (ISEVivado)PythonLinuxSPII2CMDIOhigh speed SERDESXilinx Ultrascale+Synopsys VCSSynplifyCadence AllegroDxDesigner
team collaborationtechnical leadershipcommunicationproblem solving
Industry Telecom
Job Function Design and verify FPGA hardware for Acacia products
Role Subtype FPGA Design Engineer
Tech Domains Linux, Python, Kubernetes, Docker, SQL / PostgreSQL
Hardware FPGA Design EngineerAcaciaHybridVerilog RTL codingXilinx design tool chainVivadoISEPythonLinuxSPII2CMDIOSERDESXilinx Ultrascale+Synopsys VCSSynplifyCadence AllegroDxDesignerembedded MCUslab bring uppowerboard levelopampsdacsadcsFPGA designVerilog RTLXilinx VivadoXilinx ISE

Bachelor's degree in Electrical Engineering or related field, 8+ years related experience or equivalent

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