Position Details
About this role
FPGA design engineer responsible for design/verification of FPGA blocks for Acacia product line, including Verilog RTL coding, Python-based test development, and Xilinx tool flow.
Key Responsibilities
- Design/Verify FPGAs
- Write Python tests
- FPGA emulation
- Contribute to RTL code
- Collaborate with cross-functional teams
Technical Overview
FPGA-centric hardware design with Xilinx toolchain (ISE, Vivado), Verilog RTL, high-speed interfaces, and lab bring-up; Python and Linux for test and automation.
Ideal Candidate
A high-energy FPGA design engineer with 5+ years of FPGA design/verification experience, strong Verilog RTL skills, and hands-on experience with Xilinx tools and high-speed interfaces for Acacia products.
Must-Have Skills
Nice-to-Have Skills
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Bachelor's degree in Electrical Engineering or related field, 8+ years related experience or equivalent
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