Position Details

Type Full-Time

Experience senior

Exp. Years 0

Education Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Category Engineering (Non-Software)

About this role

Integration RTL design engineer role focused on end-to-end ASIC design lifecycle, from RTL coding through tape-out, with emphasis on timing closure and SOC integration.

Key Responsibilities

RTL design & microarchitecture
Full ASIC lifecycle
Timing closure & STA
SOC integration
DFT/DFD
Cross-functional collaboration

Technical Overview

Hands-on Verilog RTL coding, STA, SDC constraints, synthesis, AMBA/PCIe/CXL interfaces, DFT/DFD features, and cross-functional collaboration across design teams.

Ideal Candidate

Senior ASIC design engineer with hands-on Verilog RTL experience and a track record across the full ASIC flow, including tape-out, SDC timing constraints, and SOC integration; strong collaboration and communication skills.

Must-Have Skills

Bachelor's or Master's degree in Electrical Engineering or Computer EngineeringProven experience with Verilog RTL codingExperience in the complete ASIC design flow: RTL -> Synthesis -> STA -> Physical Design -> Tape-outExperience writing and debugging SDC timing constraintsKnowledge of AMBA AXI/AHB/APBExperience with PCIe and CXLExperience with clock domain crossingExperience in SOC integrationStrong communication and cross-functional collaboration

Nice-to-Have Skills

2+ production ASIC tape-outsASIC/SoC tape-out experienceFormal verification toolsAI-assisted design toolsMentoring junior engineers

Required Skills

Verilog RTL coding RTL design micro-architecture specifications timing constraints (SDC) static timing analysis STA Synthesis AMBA AXI/AHB/APB PCIe CXL DFT DFD SOC integration clock domain crossing

Hard Skills

Verilog RTL codingRTL designmicro-architecture specificationstiming constraints (SDC)static timing analysis (STA)SynthesisAMBA AXI/AHB/APBPCIeCXLDFTDFDSOC integrationclock domain crossingdesign-for-test (DFT)design-for-debug (DFD)PythonPerlTcl

Soft Skills

ownershipmentorshipcommunicationcollaborationproblem solving

Industry & Role

Industry Manufacturing

Job Function Own RTL design and integration for complex ASICs

Role Subtype ASIC design engineer

Keywords for Your Resume

rtl designverilogrtl codingsynthesisstastatic timing analysissd c timing constraintsclock domain crossingam ba ax i/ahb/apbpci ecxldf tdfdsoc integrationpost-silicon validationpythonperltclVerilog RTL codingRTL designSynthesisSTAAMBA AXI/AHB/APBPCIeCXLDFT

Deal Breakers

Lack of Verilog RTL coding experience, No ASIC tape-out experience, Inability to work hybrid/onsite in San Jose

Apply for this Position →

Get matched to jobs like this

Luna finds roles that fit your skills and career goals — no endless scrolling required.

Create a Free Profile

Untitled Position

Get matched to jobs like this