About this role
Physical Design PPA role focusing on method optimization, PD co-development, and power/ timing sign-offs for high-performance cores and GPUs.
Key Responsibilities
- Drive PVT targets
- PD co-development
- Power/clock sign-off
- Power analysis
- Scripting for automation
- Global PD methodologies
Technical Overview
Emphasis on STA, PVT, clk distribution, and power analysis tools; requires scripting proficiency and CAD tool mastery for high-performance design.
Ideal Candidate
Mid-level physical design engineer with hands-on experience in timing closure, power analysis, and PD co-development across sub-micron processes; strong scripting skills and cross-functional collaboration abilities.
Must-Have Skills
MS/PhD in Electrical Engineering preferredMastery of logiccircuit designand CAD tools for high-performance designExperience with STA methodologies for timing closureExperience with timing closureOCV and other advanced statistical margining techniques
Nice-to-Have Skills
Design experience in sub-micron processesFamiliarity with CPU and/or GPU architectureHands on power-analysis and measurement tools like Prime Power and Power-ArtistScripting in Python/Perl/TclData analysis and interpretation
Required Skills
PVT cornersfrequency targetsIP physical implementationRTLPD co-developmentpower-consumptionPower analysisPrime PowerPower-ArtistSTA methodologiesclock distributionclock skewPerlTclPython
Hard Skills
PVT cornersfrequency targetsIP physical implementationRTLPD co-developmentpower-consumptionPower analysisPrime PowerPower-ArtistSTA methodologiesclock distributionclock skewscripting (Perl/Tcl/Python)
Soft Skills
attention to detailanalytical thinkingcross-functional collaborationcommunicationproblem solving
Keywords for Your Resume
physical design methodologiesPVT cornersfrequency targetsIP physical implementation recipesRTLPD co-developmentpower-consumptionPower analysisPrime PowerPower-ArtistSTA methodologiesclock distributionclock skewPerlTclPythonwafer scaletiming closureadvanced statistical marginingsub-micron design
Deal Breakers
Lack of STA timing-closure experience, No exposure to PD co-development, Reluctance to work in hybrid Austin environment
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