✦ Luna Orbit — Engineering (Non-Software)

Untitled Position

at Company

Unknown Posted March 30, 2026
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Position Details

Type Full-Time
Experience senior
Exp. Years 7+ years
Education Not specified
Category Engineering (Non-Software)

About this role

Senior ASIC design infrastructure and methodologies engineer at Annapurna Labs; focuses on automating design flows and building large-scale solutions to accelerate silicon development; collaborates with architects, designers, verification engineers, and cross-functional teams to refine flows.

Key Responsibilities

  • Develop and implement new methodologies and infrastructure to empower design teams
  • Enhance and build design flows to boost productivity
  • Collaborate with vendors to evaluate and qualify new design tools and updated tool versions
  • Collaborate with architects, designers, verification engineers, and cross-functional team members to refine existing design flows
  • Drive automation solutions to streamline flows and elevate overall design quality

Technical Overview

Scope includes RTL design, front-end methodologies, tool evaluation, and automation for Post-Silicon Flow; involves creating and maintaining automation frameworks, post-silicon validation, and SOC bring-up.

Ideal Candidate

The ideal candidate is a senior ASIC design infrastructure engineer with 7+ years in ASIC implementation, synthesis, STA, and physical design; strong in RTL, C/SystemC, and scripting; experienced with automation frameworks and Post-Silicon Flow.

Must-Have Skills

ASIC implementationsynthesisSTAphysical designdigital design in communication systemsfull-custom analog or RF layoutwireless communications systems and implementationautomation frameworks for Post-Silicon Flowverification in communication systemsUVMCSystemCscriptingRTL codingSOC bring-uppost-silicon validation

Nice-to-Have Skills

Master's degree or Ph.D. degree in Electrical Engineering or related fieldExperience in RTL coding and debugas well as performancepowerarea analysis and trade-offsExperience with modern ASIC/FPGA design and verification toolsExperience with SOC bring-up and post-silicon validation

Required Skills

ASICRTL designsynthesisSTAphysical designdigital design in communication systemsfull-custom analog or RF layoutwireless communications systems and implementationautomation frameworks for Post-Silicon Flowverification in communication systemsUVMCSystemCscriptingRTL codingSOC bring-uppost-silicon validationFPGA designdesign flowsfront-end methodologies

Hard Skills

ASICRTL designsynthesisSTAphysical designfront-end methodologiesautomation frameworksPost-Silicon FlowverificationUVMCSystemCscriptingRTL codingSOC bring-uppost-silicon validationFPGA designdesign toolsverification tools

Soft Skills

collaborationcommunicationteamworkproblem-solvinginitiativeautomation mindsetcross-functional collaboration

Industry & Role

Industry SaaS
Job Function Lead ASIC design infrastructure and methodologies to accelerate silicon development and improve design quality
Role Subtype ASIC design engineer

Keywords for Your Resume

ASICASIC Design MethodologiesRTL designsynthesisSTAphysical designfront-end methodologiesautomation frameworksPost-Silicon FlowverificationUVMCSystemCscriptingRTL codingSOC bring-uppost-silicon validationFPGA designdesign toolsverification tools

Deal Breakers

Lacks 5+ years of UVM/C/SystemC/scripting experience, Lacks 7+ years of ASIC implementation, synthesis, STA and physical design, No experience with ASIC/FPGA tools

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