Position Details
About this role
Seeking a Lead Emulation Engineer to develop and manage emulation strategies for AI inference ASICs, bridging hardware and software verification environments.
Key Responsibilities
- Define emulation strategy
- Manage emulation environment
- Bridge hardware and software teams
- Lead verification team
- Debug complex SoC issues
Technical Overview
Environment involves ASIC/SoC verification, emulation using Cadence Palladium systems, SystemVerilog, UVM, with knowledge of high-speed interfaces like PCIe, CXL, DDR5, and scripting in Python and Tcl.
Ideal Candidate
The ideal candidate is an experienced ASIC/SoC verification engineer with at least 8 years of hands-on emulation and verification experience, proficient with Cadence Palladium systems, SystemVerilog, and UVM. They are proactive leaders capable of managing complex verification environments remotely.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Less than 8 years of ASIC/SoC verification experience, Lack of experience with Cadence Palladium, No knowledge of SystemVerilog or UVM, Inability to work remotely
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