✦ Luna Orbit — AI & Machine Learning

Machine Learning Engineer Jobs in Chicago

at Builtinchicago

Remote Posted March 17, 2026
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Position Details

Type Not Specified
Experience senior
Exp. Years Not specified
Education Not specified
Category AI & Machine Learning

About this role

This role involves designing and deploying machine learning inference engines on FPGA/ASIC hardware, optimizing neural networks, and working on hardware-software co-design remotely in fintech and research sectors.

Key Responsibilities

  • Design ML inference engines
  • Optimize neural networks for FPGA/ASIC
  • Implement hardware-software co-design
  • Deploy low-latency AI models
  • Collaborate on hardware acceleration projects

Technical Overview

The technical scope includes FPGA/ASIC hardware design, neural network optimization, RTL development, and deployment using tools like Quartus and Vivado, with expertise in C++, Verilog, and VHDL.

Ideal Candidate

The ideal candidate is a senior ML engineer with expertise in FPGA, ASIC, and neural network deployment, proficient in C++, Python, Verilog, and VHDL, capable of designing and optimizing ML inference engines on hardware platforms remotely.

Must-Have Skills

C++FpgaPythonVerilogVhdl

Nice-to-Have Skills

AsicQuartusRtlSynplifyVivadoLarge Language ModelsNLPModel OptimizationModel QuantizationPrompt Engineering

Tools & Platforms

QuartusVivadoSynplify

Required Skills

C++FPGAPythonVerilogVhdlLarge Language ModelsModel OptimizationModel QuantizationPrompt Engineering

Hard Skills

AsicC++FpgaPythonQuartusRtlSynplifyVerilogVhdlVivadoLarge Language ModelsNLPModel OptimizationModel QuantizationPrompt Engineering

Soft Skills

designimplementationdeploymentoptimizationcollaboration

Industry & Role

Industry Fintech, Software, Healthtech, Research
Job Function Designing and deploying hardware-accelerated machine learning models
Role Subtype ML Engineer
Tech Domains Fpga, Verilog, Vhdl, Quartus, Vivado, Synplify

Keywords for Your Resume

ML EngineerAI EngineerNLP EngineerFPGAASICC++PythonVerilogVhdlLarge Language ModelsModel OptimizationModel QuantizationPrompt EngineeringHardware AccelerationML inference enginesNeural NetworksRTLFPGA deploymentQuantizationFpga

Deal Breakers

Lack of FPGA or ASIC experience, No proficiency in C++, Verilog, or VHDL, Inability to work remotely, No experience with neural network optimization

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