Position Details

Type Full-Time

Experience senior

Exp. Years 8+ years

Education BS/MS in EE, CS, CSE (or similar)

Category Engineering (Non-Software)

About this role

This role is a technical expert for VLSI physical design leadership supporting AMD’s next generation cores and caches. You will optimize power, performance, area, and schedule and lead solutions for complex design and tool problems through sign-off.

Key Responsibilities

Technical lead for high-speed VLSI design in deep sub-micron processes
Optimize power, performance, area, and schedule with RTL and physical designers
Solve design and tool problems and create technical presentations
Guide and mentor junior engineers
Apply chip-level floor planning through sign off (STA, parasitic extraction, IR drop, electromigration, physical verification)

Technical Overview

You will lead high-speed VLSI physical design in deep sub-micron processes, collaborating with RTL and physical designers to optimize PPA and meet schedules. Responsibilities span chip-level floor planning, bus/pin planning, clock tree synthesis, placement, routing, parasitic extraction, static timing analysis, IR drop analysis, electromigration checks, and physical verification and sign-off.

Ideal Candidate

The ideal candidate is a senior microprocessor physical design engineer with 8+ years of hardware design experience focused on high-speed VLSI in deep sub-micron processes. They have hands-on expertise in chip-level floor planning through sign-off, including STA, parasitic extraction, IR drop analysis, and electromigration, and they can lead technical problem solving across design and tool challenges.

Must-Have Skills

high-speed VLSI designdeep sub-micron processescomputer architecture8+ years hardware design experience

Nice-to-Have Skills

Hands-on experience in high-speed VLSI designExcellent understanding of computer architecturehardware concepts & design tradeoffs requiredKnowledge of Chip Level Floor planningBus / Pin PlanningClock Tree SynthesisPlacementOptimizationRoutingParasitic ExtractionStatic Timing AnalysisIR drop analysiselectromigrationPhysical Verification and Sign OffKnowledge of digital circuitshigh speed flopssynchronizerslevel shiftersand SRAMFamiliar with programing languages such as PerlCtcletc.

Required Skills

high-speed VLSI designdeep sub-micron processespower performance area schedule optimizationChip Level Floor planningBus / Pin PlanningClock Tree SynthesisPlacementRoutingParasitic ExtractionStatic Timing AnalysisIR drop analysiselectromigrationPhysical Verification and Sign OffVerilog RTLdigital circuitshigh speed flopssynchronizerslevel shiftersSRAMPerlCtcl

Hard Skills

high-speed VLSI designdeep sub-micron processesRTL and physical design optimizationpowerperformanceareaschedule optimizationcomputer architecturehardware conceptsdesign tradeoffsChip Level Floor planningBus / Pin PlanningClock Tree SynthesisPlacementOptimizationRoutingParasitic ExtractionStatic Timing AnalysisIR drop analysiselectromigrationPhysical Verification and Sign OffVerilog RTLcomprehend complex Verilog RTLminor modifications for timing or powerdigital circuitshigh speed flopssynchronizerslevel shiftersSRAMprogramming languagesPerlCtcl

Soft Skills

analytical thinkingproblem-solving skillsattention to detailsself-motivationcommitment to meeting deadlinescreativityinnovationexcellent verbal and written communication skillstechnical presentationsteamworkleadershipmentor junior engineers

Industry & Role

Industry Manufacturing

Job Function Lead microprocessor VLSI physical design from floor planning through sign-off

Role Subtype Electrical Engineer

Tech Domains Linux, Python, Azure, VMware, Networking / TCP-IP

Clearance & Visa

Visa Sponsorship No

Keywords for Your Resume

Microprocessor Physical Design EngineerVLSI physical design engineerhigh-speed VLSI designdeep sub-micron processesRTL and physical designerspowerperformanceareascheduleChip Level Floor planningBus / Pin PlanningClock Tree SynthesisPlacementOptimizationRoutingParasitic ExtractionStatic Timing AnalysisIR drop analysiselectromigrationPhysical Verification and Sign OffVerilog RTLdigital circuitshigh speed flopssynchronizerslevel shiftersSRAMPerlCtclmentor junior engineers

Deal Breakers

8+ years hardware design experience, Experience with high-speed VLSI design in deep sub-micron processes

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