Position Details

Salary $108K – $172K USD / year

Type Full-Time

Experience mid

Exp. Years 8+ years

Education Bachelor's degree in Electrical or Electronics Engineering

Category Engineering (Non-Software)

About this role

This role involves leading physical design activities for advanced ICs, including RTL synthesis, verification, and tape-out, utilizing scripting and EDA tools.

Key Responsibilities

Execute physical design
Perform RTL synthesis
Ensure timing closure
Develop flows and methodologies
Collaborate on layout and verification

Technical Overview

The position requires expertise in VLSI design, physical implementation, scripting in TCL and PERL, and experience with EDA tool flows for ASIC development.

Ideal Candidate

The ideal candidate is an experienced physical design engineer with at least 8 years of experience in RTL to tape-out processes, proficient in scripting languages TCL and PERL, and skilled in using EDA tools for ASIC and VLSI design.

Must-Have Skills

Full physical design cycle experienceRTL to Tape-outScripting in TCL and PERLProficiency in EDA toolsMinimum 8 years experience

Nice-to-Have Skills

Flow and methodology developmentClock Tree SynthesisFloor-planningLayout optimization

Tools & Platforms

EDA Tools

Required Skills

Physical DesignRTL SynthesisPhysical VerificationTiming ClosurePlace and RouteFloor-planningLayout DesignFlow DevelopmentEDA ToolsScripting TCLScripting PERL

Hard Skills

Physical DesignRTL SynthesisPhysical VerificationTiming ClosurePlace and RouteFloor-planningLayout DesignFlow DevelopmentEDA ToolsScripting (TCLPERL)

Soft Skills

Verbal CommunicationWritten CommunicationCollaborationProblem-solvingAttention to Detail

Industry & Role

Industry Technology / Semiconductors

Job Function Physical design and tape-out of integrated circuits

Role Subtype Physical Design Engineer

Tech Domains Semiconductors

Keywords for Your Resume

Physical DesignRTL SynthesisPhysical VerificationTiming ClosurePlace and RouteFloor-planningLayout DesignFlow DevelopmentEDA ToolsScripting TCLScripting PERLASIC DesignTape-outIC DesignHardware DesignVLSIVerilogDigital Designphysical designRTL synthesisphysical verificationtiming closureplace and routefloor-planninglayout designEDA toolsTCL scriptingPERL scripting

Deal Breakers

Less than 8 years of experience, Lack of full physical design cycle experience, No scripting in TCL or PERL, No proficiency in EDA tools

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