About this role
Broadcom seeks a senior ASIC physical design engineer to work on SerDes connectivity ASICs for integrated data center products. The role focuses on deep physical design implementation knowledge, constraint specification, and verification/debug across chip and block levels.
Key Responsibilities
- Develop and implement power-grid and high speed clock constraints and specification
- Execute physical design with physical aware synthesis, floorplanning, CTS, and place and route
- Use physical design verification methodology to debug LVS/DRC at chip and block level
- Perform CDC and static timing analysis using relevant tools
- Use SDF annotated simulations and understand parasitic delays in mixed signal environments
Technical Overview
You will apply physical aware synthesis, floorplanning, CTS, and place-and-route while developing power-grid and high speed clock constraints. The position includes physical verification methodology (LVS/DRC), CDC and static timing analysis, SDF annotated simulations with parasitic delay awareness, and tool usage including Virtuoso, Caliber, and Redhawk for power analysis.
Ideal Candidate
The ideal candidate is a senior ASIC physical design engineer with 6+ years of physical design experience, including physical aware synthesis, floorplanning, CTS, and place and route. They have strong verification/debug skills for LVS/DRC, CDC and static timing analysis experience, and tool familiarity with Virtuoso, Caliber, and Redhawk for power analysis, plus scripting in Perl/Python/tcl/shell to automate flows.
Must-Have Skills
MS in Electrical Engineering or Computer Engineering with 6+ years of experience in Physical designDeep knowledge about industry standards in Physical DesignPhysical aware synthesisFloorplanningCTS and place and routeExperience in developing and implementing Power-grid and high speed clock constraints and specificationGood understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block levelExperience with CDCstatic timing analysis methodologies and relevant toolsExposure to SDF annotated simulations with good understanding of parasitic delaysUnderstanding and experience of mixed signal environments is a mustFamiliar with VirtuosoCaliber & Redhawk (power analysis) toolsGood understanding of design tape-out to foundriesSolid understanding of supply chain for IC Product developmentScripting experience with PerlPythontclshell and drive to automate flows
Nice-to-Have Skills
Understanding of backend Cadence toolsDeep understanding of Signal Integrity and Power Integrity for High Speed designsProactivecollaborative and creative approach to innovationtechnical development and consensus facilitation to influence optimal project resultsExcellent time and task managementand interpersonal skills
Tools & Platforms
VirtuosoCaliberRedhawkCadence
Required Skills
Physical designPhysical aware synthesisFloorplanningCTSplace and routePower-grid and high speed clock constraintsphysical design verification methodologyLVS/DRCCDCstatic timing analysisSDF annotated simulationsparasitic delaysmixed signal environmentsVirtuosoCaliberRedhawk (power analysis)design tape-out to foundriessupply chain for IC Product developmentPerlPythontclshellautomate flowsbackend Cadence toolsSignal IntegrityPower Integrity
Hard Skills
Physical designPhysical aware synthesisFloorplanningClock Tree Synthesis (CTS)Place and routePower-grid and high speed clock constraints and specificationPhysical design verification methodologyLVS/DRCCDCStatic timing analysis (STA)static timing analysis methodologies and relevant toolsSDF annotated simulationsparasitic delaysMixed signal environmentsVirtuosoCaliberRedhawk (power analysis)back-end Cadence toolsSignal IntegrityPower IntegritySignal Integrity and Power Integrity for High Speed designsdesign tape-out to foundriessupply chain for IC Product developmentPerlPythontclshellscripting experience to automate flows
Soft Skills
Proactivecollaborative and creative approach to innovationConsensus facilitationExcellent time and task managementInterpersonal skills
Keywords for Your Resume
Physical Design Engineersenior level ASIC physical design engineerPhysical designPhysical aware synthesisFloorplanningCTSClock Tree Synthesis (CTS)place and routePower-gridhigh speed clock constraintsphysical design verification methodologyLVSDRCCDCstatic timing analysisSTASDF annotated simulationsparasitic delaysmixed signal environmentsVirtuosoCaliberRedhawkpower analysisdesign tape-out to foundriessupply chain for IC Product developmentPerlPythontclshellautomate flowsElectrical EngineeringComputer Engineering6+ years
Deal Breakers
MS in Electrical Engineering or Computer Engineering with 6+ years of Physical design experience, Mixed signal environments understanding is a must, Familiar with Virtuoso, Caliber & Redhawk (power analysis) tools, Scripting experience with Perl, Python, tcl, shell to automate flows
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