About this role
This role is for a senior ASIC physical design engineer supporting SerDes connectivity ASICs for highly integrated data center products. You will own key physical design activities such as floorplanning, CTS, place and route, and timing/constraint validation, including power-grid and high speed clock constraint work.
Key Responsibilities
- Develop and implement Power-grid and high speed clock constraints
- Perform floorplanning, CTS, and place and route
- Apply physical design verification methodology to debug LVS/DRC
- Use CDC and static timing analysis methodologies and tools
- Work with SDF annotated simulations and parasitic delays in mixed signal environments
Technical Overview
The position requires deep physical design knowledge (including physical aware synthesis), constraint development for power-grid and high speed clocking, and debug capability for LVS/DRC issues. You will use timing analysis approaches including CDC and static timing analysis and work with SDF annotated simulations while supporting mixed-signal environments using tools such as Virtuoso, Caliber, and Redhawk.
Ideal Candidate
The ideal candidate is a senior ASIC physical design engineer with 6+ years of physical design experience, including power-grid and high speed clock constraint development as well as expertise in floorplanning, CTS, and place and route. They can debug LVS/DRC issues using physical design verification methodologies and have strong timing analysis experience with CDC and static timing analysis, including SDF annotated simulations. They are tool-competent with Virtuoso, Caliber, and Redhawk and have automation scripting experience in Perl, Python, tcl, and shell.
Must-Have Skills
MS in Electrical Engineering or Computer Engineering with 6+ years of experience in Physical designDeep knowledge about industry standards in Physical DesignPhysical aware synthesisFloorplanningCTS and place and routeExperience in developing and implementing Power-grid and high speed clock constraintsGood understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block levelExperience with CDCstatic timing analysis methodologies and relevant toolsExposure to SDF annotated simulations with good understanding of parasitic delaysUnderstanding and experience of mixed signal environments is a mustCandidates must be familiar with VirtuosoCaliber & Redhawk (power analysis) toolsGood understanding of design tape-out to foundries and solid understanding of supply chain for IC Product developmentScripting experience with PerlPythontclshell and drive to automate flowsExcellent time and task managementinterpersonal skills
Nice-to-Have Skills
Understanding of backend Cadence toolsDeep understanding of Signal Integrity and Power Integrity for High Speed designsProactivecollaborative and creative approach to innovationtechnical development and consensus facilitation to influence optimal project results
Tools & Platforms
VirtuosoCaliberRedhawkCadence toolsPerlPythontclshell
Required Skills
Physical designPhysical aware synthesisFloorplanningCTSplace and routePower-grid constraintshigh speed clock constraintsphysical design verification methodologyLVSDRCCDCstatic timing analysisSDF annotated simulationsparasitic delaysmixed signal environmentsVirtuosoCaliberRedhawk (power analysis)tape-out to foundriessupply chain for IC Product developmentScripting (PerlPythontclshell)automate flows
Hard Skills
ASIC physical designSerDes connectivity ASICsPhysical aware synthesisFloorplanningClock Tree SynthesisPlace and routePower-gridpower-grid constraintshigh speed clock constraintsphysical design verification methodologyLVSDRCCDCstatic timing analysis methodologiesstatic timing analysisSDF annotated simulationsparasitic delaysmixed signal environmentsVirtuosoCaliberRedhawk (power analysis)backend Cadence toolsSignal IntegrityPower Integritydesign tape-out to foundriesIC Product development supply chainScriptingPerlPythontclshellRTLCTSPlace and Route
Soft Skills
Proactivecollaborative and creative approachconsensus facilitationExcellent time and task managementinterpersonal skills
Keywords for Your Resume
Physical Design EngineerPhysical designASIC physical design engineerSerDes connectivity ASICsPhysical aware synthesisFloorplanningCTSClock Tree Synthesisplace and routePower-grid constraintshigh speed clock constraintsphysical design verification methodologyLVSDRCCDCstatic timing analysisSDF annotated simulationsparasitic delaysmixed signal environmentsVirtuosoCaliberRedhawkpower analysistape-outfoundriessupply chain for IC Product developmentPerlPythontclshellautomate flows
Deal Breakers
MS in Electrical Engineering or Computer Engineering with 6+ years of experience in Physical design, Must be familiar with Virtuoso, Caliber & Redhawk (power analysis) tools, Must have scripting experience with Perl, Python, tcl, shell and automate flows, Understanding and experience of mixed signal environments is a must, Experience with CDC and static timing analysis methodologies and relevant tools
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