Position Details
About this role
This role involves leading the physical design process for advanced ICs, including RTL synthesis, placement, routing, verification, and tape-out, primarily for data center and AI/ML applications.
Key Responsibilities
- Execute physical design, Synthesize RTL, Perform physical verification, Achieve timing closure, Collaborate with RTL engineers
Technical Overview
The technical environment includes physical design tools, scripting in TCL and PERL, and collaboration with IC RTL engineers to deliver silicon tape-outs for high-performance semiconductor products.
Ideal Candidate
The ideal candidate is a senior physical design engineer with over 8 years of experience in RTL to tape-out processes, proficient in scripting and EDA tools, and capable of leading physical verification and timing closure for advanced semiconductor projects.
Must-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of full physical design cycle experience, No proficiency in scripting languages TCL/PERL, No experience with physical verification tools, Less than 8 years of relevant experience
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