Position Details
About this role
This role involves developing physical design methodologies for advanced semiconductor nodes, ensuring design quality and silicon success.
Key Responsibilities
- Physical design and signoff methodology development for advanced nodes
- Full chip timing analysis
- Clock tree synthesis and analysis
- Formal verification and physical verification
- Developing ML and data analysis solutions
Technical Overview
Focus on ASIC physical design, signoff methodologies, static timing analysis, and integrating ML applications into design flows using tools like Synopsys and Cadence.
Ideal Candidate
The ideal candidate is a mid-level ASIC Physical Design engineer with experience in advanced node processes, physical verification, and scripting. They should be detail-oriented, collaborative, and proficient with industry-standard tools like Synopsys and Cadence.
Must-Have Skills
Nice-to-Have Skills
Tools & Platforms
Required Skills
Hard Skills
Soft Skills
Industry & Role
Keywords for Your Resume
Deal Breakers
Lack of experience with Place and Route tools, No experience in advanced node technologies (5nm and below), Absence of scripting skills (TCL, Perl, Python)
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