Position Details

Salary $120K – $192K USD / year

Type Not Specified

Experience mid

Exp. Years 8+ years

Education Bachelor's degree in Electrical Engineering or Computer Engineering

Category Engineering (Non-Software)

About this role

Full-chip static timing analysis engineer responsible for ensuring ASIC meets performance and timing requirements across all conditions, managing constraints, and automating analysis workflows.

Key Responsibilities

Own timing sign-off
Develop constraints
Manage multi-corner analysis
Automate timing flows
Implement ECOs

Technical Overview

Environment involves industry-standard sign-off tools, scripting in Tcl, Python, Perl, and advanced timing analysis including on-chip variation and multi-corner scenarios.

Ideal Candidate

The ideal candidate is an experienced ASIC timing engineer with at least 8 years of hands-on experience in static timing analysis, timing closure, and constraint development. They are proficient in scripting languages and familiar with sign-off tools from Cadence or Synopsys.

Must-Have Skills

ASIC STATiming closureConstraint developmentScripting (TclPythonPerl)Sign-off tools

Nice-to-Have Skills

On-Chip Variation (AOCV/POCV)Signal IntegrityIR-drop analysisMulti-Mode Multi-Corner (MMMC)Timing ECOs

Tools & Platforms

CadenceSynopsysTclPythonPerl

Required Skills

Static Timing AnalysisASIC timing closureConstraint developmentScripting (TclPythonPerl)Sign-off toolsAOCVPOCVSignal IntegrityIR-dropMMMCTiming ECOs

Hard Skills

Static Timing Analysis (STA)ASIC timing closureConstraint developmentScripting (TclPythonPerl)Sign-off tools (CadenceSynopsys)On-Chip Variation (AOCV/POCV)Signal IntegrityIR-drop analysisMulti-Mode Multi-Corner (MMMC) analysisTiming ECOsAutomation scripting

Soft Skills

Problem solvingTeam collaborationCommunicationAttention to detailTechnical documentation

Industry & Role

Industry Semiconductor/ASIC Design

Job Function ASIC timing analysis and sign-off engineering

Keywords for Your Resume

Physical Design Timing EngineerStatic Timing AnalysisASIC timing closureConstraint developmentSign-off toolsOn-Chip VariationAOCVPOCVSignal IntegrityIR-dropMulti-Mode Multi-CornerTiming ECOsScriptingTclPythonPerlASIC STATiming closure

Deal Breakers

Less than 8 years of ASIC timing experience, No experience with sign-off tools, Lack of scripting skills (Tcl, Python, Perl), Inability to handle multi-corner analysis, Location outside San Jose, CA

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Physical Design Timing Engineer (STA)

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