Position Details

Salary $141K – $226K USD / year

Type Not Specified

Experience senior

Exp. Years 12+ years of hands-on experience

Education Bachelor's degree in Electrical Engineering or Computer engineering

Category Engineering (Non-Software)

About this role

Physical Design Timing Engineer (STA) role responsible for ensuring an ASIC meets performance and timing targets across all operating conditions. The engineer owns full-chip timing sign-off, constraint development, MMMC analysis, and automated Timing ECOs to resolve timing violations.

Key Responsibilities

Own final timing closure for ASIC with quality checks across PVT corners
Author and maintain SDC for functional and test modes (Scan, MBIST, ATPG)
Analyze AOCV/POCV, Signal Integrity (crosstalk), and IR-drop aware STA
Manage MMMC analysis for hundreds of timing scenarios
Automate, generate, and implement Timing ECOs to fix setup, hold, and transition violations

Technical Overview

This position focuses on ASIC Static Timing Analysis (STA) using SDC and MMMC techniques to manage hundreds of timing scenarios across PVT corners. You will use Tcl (primary) along with Python/Perl/Shell for scripting and ECO automation, working with RTL, Physical Design, and DFT teams and using Cadence or Synopsys sign-off tools.

Ideal Candidate

The ideal candidate is a senior ASIC Static Timing Analysis (STA) engineer with 12+ years of hands-on experience in timing closure and timing constraints development, including authoring and maintaining SDC. They have deep expertise in MMMC (Multi-Mode Multi-Corner) analysis, PVT corners sign-off, and advanced timing concepts like AOCV/POCV and IR-drop aware STA. They are highly proficient in Tcl (primary), with experience automating ECOs using scripting and working across RTL, Physical Design, and DFT teams using Cadence or Synopsys tools.

Must-Have Skills

ASIC STA and timing constraints developmenttiming closure with Cadence or Synopsys toolsauthorvalidateand maintain SDCFull-Chip Timing Sign-offMulti-Mode Multi-Corner (MMMC) AnalysisScripting languages like Tcl (primary for EDA tools)PythonPerlor ShellA minimum of 12 years of hands-on experience in ASIC STA and timing constraints development

Nice-to-Have Skills

IR-drop aware STASignal Integrity (crosstalk)Advanced Timing Concepts knowledge (AOCV/POCV)

Tools & Platforms

Static Timing Analysis (STA)SDCTclPythonPerlShellCadenceSynopsysRTLPhysical DesignDFT

Required Skills

Static Timing Analysis (STA)ASIC timing closureSDC constraint developmentPVT cornersScanMBISTATPGOn-Chip Variation (AOCV/POCV)Signal Integrity (crosstalk)IR-drop aware STAMulti-Mode Multi-Corner (MMMC) AnalysisTiming ECOsTcl scriptingPythonPerlShellRTLPhysical DesignDFTCadenceSynopsys

Hard Skills

ASICStatic Timing Analysis (STA)timing closureFull-Chip Timing Sign-offtiming requirementsprocessvoltageand temperature (PVT) cornersSDCConstraint Developmentfunctional and test modesScanMBISTATPGfoundry guidelinessign off cornersmarginsderatesOn-Chip Variation (AOCV/POCV)Signal Integrity (crosstalk)IR-drop aware STAMulti-Mode Multi-Corner (MMMC) Analysistiming scenariosTiming ECOssetup violationshold violationstransition violationsECO automationTclPythonPerlShellcross-functional collaborationRTLPhysical DesignDFTguard-banding requirementspower/performance and area tradeoffsEDA tool expertiseCadenceSynopsysScriptingEnglish communicationclear and precise communication skillsdocument best practices and lessons learned

Soft Skills

problem solving skillsattention to every technical aspectteam playerclear and precise communication skillsdocumentation disciplinecross-functional collaboration

Industry & Role

Industry Aerospace

Job Function Perform full-chip ASIC static timing analysis and timing closure using MMMC and SDC

Role Subtype Mechanical Engineer

Tech Domains Linux, Python, Java, Kubernetes, Cybersecurity

Keywords for Your Resume

Physical Design Timing EngineerSTAStatic Timing AnalysisFull-Chip Timing Sign-offtiming closureASICSDCConstraint DevelopmentPVT cornersprocessvoltageand temperature (PVT) cornersScanMBISTATPGfoundry guidelinessign off cornersmarginsderatesOn-Chip Variation (AOCV/POCV)Signal Integrity (crosstalk)IR-drop aware STAMulti-Mode Multi-Corner (MMMC) AnalysisTiming ECOssetup violationshold violationstransition violationsTclPythonPerlShellRTLPhysical DesignDFTCadenceSynopsys

Deal Breakers

A minimum of 12 years of hands-on experience in ASIC STA and timing constraints development, Timing closure experience with Cadence or Synopsys tools, Must be proficient with scripting languages including Tcl (primary)

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