Position Details

Salary $120K – $192K USD / year

Type Full-Time

Experience senior

Exp. Years 8+ years

Education Bachelor's degree in Electrical Engineering or Computer Engineering

Category Engineering (Non-Software)

About this role

This role involves ensuring ASIC designs meet performance and timing requirements through static timing analysis, constraint development, and sign-off procedures.

Key Responsibilities

Own timing sign-off
Develop and validate constraints
Perform timing closure
Automate ECOs
Collaborate with RTL and physical design teams

Technical Overview

Expertise in ASIC STA, scripting in Tcl and Python, industry-standard sign-off tools like Cadence and Synopsys, and advanced timing analysis techniques.

Ideal Candidate

The ideal candidate is a senior ASIC STA engineer with at least 8 years of experience in timing closure, constraints development, and scripting. They are proficient with industry-standard sign-off tools and have deep knowledge of on-chip variation and multi-corner analysis.

Must-Have Skills

ASIC STATiming constraints developmentTiming closureScripting in Tcl and PythonExperience with Cadence or Synopsys tools

Nice-to-Have Skills

On-Chip VariationMulti-Mode Multi-Corner analysisSign-off toolsTiming ECOs

Tools & Platforms

CadenceSynopsysTclPythonPerl

Required Skills

ASICStatic Timing AnalysisSTATiming closureScriptingTclPythonPerlCadenceSynopsysTiming ECOs

Hard Skills

ASICStatic Timing AnalysisSTAScriptingTclPythonPerlCadenceSynopsysTiming closureOn-Chip VariationAOCVPOCVSign-off tools

Soft Skills

Problem solvingCommunicationCollaborationAttention to detailTeamwork

Industry & Role

Industry Semiconductor / Electronics

Job Function ASIC timing analysis and closure engineering

Keywords for Your Resume

ASICStatic Timing AnalysisSTATiming closureTiming constraintsScriptingTclPythonPerlCadenceSynopsysOn-Chip VariationAOCVPOCVSign-off toolsTiming ECOsASIC STAScripting in Tcl and PythonCadence or Synopsys toolsMulti-Mode Multi-Corner analysis

Deal Breakers

Less than 8 years of ASIC STA experience, Lack of scripting skills in Tcl or Python, No experience with Cadence or Synopsys tools

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Physical Design Timing Engineer (STA)

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