About this role
This role owns full-chip static timing analysis sign-off and timing closure for ASIC performance across PVT corners. You will develop and maintain timing constraints (SDC), analyze on-chip variation and signal integrity, and automate timing ECOs to fix timing violations.
Key Responsibilities
- Own final timing closure for ASIC across PVT corners
- Author/validate/maintain SDC for various modes including Scan, MBIST, ATPG
- Apply advanced STA concepts (AOCV/POCV, signal integrity, IR-drop aware STA)
- Manage MMMC analysis and timing scenarios
- Automate timing ECOs and collaborate across RTL, Physical Design, and DFT
Technical Overview
You will perform ASIC STA with full-chip sign-off using Cadence or Synopsys sign-off tools, including SDC development for functional and test modes (Scan, MBIST, ATPG). The scope includes AOCV/POCV, crosstalk and IR-drop aware STA, MMMC analysis for hundreds of timing scenarios, and scripting-heavy ECO automation using Tcl (primary), Python, Perl, and Shell.
Ideal Candidate
The ideal candidate is a senior ASIC STA engineer with 12+ years of hands-on experience in full-chip static timing analysis and timing constraints development. They have strong timing closure experience using Cadence or Synopsys sign-off tools, deep expertise in AOCV/POCV, signal integrity (crosstalk), IR-drop aware STA, and advanced MMMC analysis, with strong scripting in Tcl (primary), Python, and Perl.
Must-Have Skills
Bachelor's degree in Electrical Engineering or Computer engineeringA minimum of 12 years of hands-on experience in ASIC STA and timing constraints developmenttiming closure with Cadence or Synopsys toolsConstraint Development: authorvalidateand maintain SDCFull-Chip Timing Sign-off and timing closure across processvoltageand temperature (PVT) cornersAdvanced Timing Concepts: deep knowledge of On-Chip Variation (AOCV/POCV)Signal Integrity (crosstalk)and IR-drop aware STAMMMC AnalysisTiming ECOsHigh proficiency in Tcl (primary for EDA tools)Pythonand Perl
Nice-to-Have Skills
Expert proficiency in industry-standard sign-off toolMulti-mode multi-corner constraints optimizationAutomategenerate and implement ECOs
Tools & Platforms
CadenceSynopsysEDA toolsTclPythonPerlShellSDC (Synopsys Design Constraints)Full-Chip Static Timing Analysis (STA)
Required Skills
Physical Design Timing EngineerSTAFull Chip Static Timing AnalysisASIC STAtiming closurePVT cornersSDC constraint developmentScanMBISTATPGAOCV/POCVsignal integritycrosstalkIR-drop aware STAMMMC analysistiming ECOssetup/hold/transition violationsTclPythonPerlShellCadenceSynopsysRTLPhysical DesignDFTguard-banding
Hard Skills
Full-Chip Static Timing Analysis (STA)timing closurePVT cornersprocessvoltageand temperature (PVT) cornersConstraint DevelopmentSDCfunctional modestest modesScanMBISTATPGfoundry guidelinessign-off cornersmarginsderatesOn-Chip Variation (AOCV/POCV)Signal Integrity (crosstalk)IR-drop aware STAMulti-Mode Multi-Corner (MMMC) Analysistiming ECOssetup violationshold violationstransition violationsscriptingTclPythonPerlShellcross-functional collaborationRTLPhysical DesignDFTguard-banding requirementspower/performance tradeoffsarea goalsdocument best practicesindustry-standard sign-off tooltiming constraints developmentCadence toolsSynopsys tools
Soft Skills
clear and precise communicationteam playerstrong problem solving skillsattention to every technical aspect
Keywords for Your Resume
Physical Design Timing EngineerSTAFull Chip Static Timing AnalysisStatic Timing Analysis (STA)ASIC STAtiming closurePVT cornersprocess voltage temperatureConstraint DevelopmentSDCScanMBISTATPGAOCVPOCVOn-Chip VariationSignal IntegritycrosstalkIR-drop aware STAMMMCMulti-Mode Multi-Cornertiming ECOssetup violationshold violationstransition violationsTclPythonPerlShellCadenceSynopsysRTLPhysical DesignDFTguard-banding
Deal Breakers
Bachelor's degree in Electrical Engineering or Computer engineering, Minimum 12 years of hands-on experience in ASIC STA and timing constraints development, Timing closure experience with Cadence or Synopsys tools, Must have constraint development experience authoring/validating/maintaining SDC, Must have advanced STA knowledge including AOCV/POCV, signal integrity (crosstalk), and IR-drop aware STA
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