Position Details

Salary $120K – $192K USD / year

Type Full-Time

Experience senior

Exp. Years 8+ Years of relevant experience

Education Bachelor's degree required in Electrical Engineering or Electronics Engineering

Category Engineering (Non-Software)

About this role

Broadcom is hiring a Physical IC Design Engineer to own critical physical design execution from RTL through tape-out. The role emphasizes timing closure, EM/IR analysis, and full-chip physical implementation with in-person work at the San Jose site.

Key Responsibilities

Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
Setup and Synthesizing RTL
Timing closure through various methods and strategies
EM/IR Analysis
Place and Route, Clock Tree Synthesis, Floor-planning and Layout

Technical Overview

You will drive the physical design lifecycle including synthesis, physical verification, and timing closure, with hands-on work for place and route and clock tree synthesis. The work includes floorplanning/layout, EM/IR analysis, and developing flows/methodologies using EDA tooling and TCL/PERL scripting.

Ideal Candidate

The ideal candidate is an experienced ASIC physical design engineer with full RTL to tape-out experience, including timing closure, place and route, and clock tree synthesis. They have strong scripting skills with TCL/PERL and are proficient with EDA tools, along with excellent communication and the ability to work in-person at the San Jose site.

Must-Have Skills

TCL/PERL ScriptingProficiency in related EDA ToolsFull physical design cycle experience: RTL to Tape-outExecution of Physical DesignSynthesisPhysical Verificationand Timing ClosurePlace and RouteClock Tree SynthesisEM/IR AnalysisFloor-planning and Layout

Tools & Platforms

EDA ToolsTCLPERL

Required Skills

Physical DesignSynthesisPhysical VerificationTiming ClosureSetup and Synthesizing RTLTiming closureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and LayoutFlow and Methodology DevelopmentTCL/PERL ScriptingProficiency in related EDA ToolsFull physical design cycle experience: RTL to Tape-out

Hard Skills

Physical DesignSynthesisPhysical VerificationTiming ClosureSetup and Synthesizing RTLTiming closureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and LayoutFlow and Methodology DevelopmentTCL/PERL ScriptingEDA ToolsFull physical design cycle experience: RTL to Tape-outRTL (Register Transfer Level)

Soft Skills

Excellent verbal and written communication skillsCollaborating with IC Design RTL EngineersTeamwork

Industry & Role

Industry Telecom

Job Function Own ASIC physical design execution from RTL to tape-out, including timing closure and physical verification.

Role Subtype Electrical Engineer

Tech Domains Linux

Keywords for Your Resume

Physical IC Design EngineerPhysical DesignSynthesisPhysical VerificationTiming ClosureSetup and Synthesizing RTLEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and LayoutFlow and Methodology DevelopmentRTL to Tape-outTCL/PERL ScriptingTCLPERLEDA ToolsIn-personno remote work allowedSan Jose siteElectrical EngineeringElectronics Engineering8+ YearsBachelor's degree

Deal Breakers

Must be able to work in person at the San Jose site (no remote work allowed), Bachelor's degree required in Electrical Engineering or Electronics Engineering, 8+ years of relevant experience, TCL/PERL Scripting required

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