Position Details

Salary $120K – $192K USD / year

Type Not Specified

Experience senior

Exp. Years 8+ Years

Education Bachelor's degree required in Electrical Engineering or Electronics Engineering

Category Engineering (Non-Software)

About this role

This role is a Physical IC Design Engineer position responsible for taking RTL through physical design execution to tape-out. You will drive timing closure and physical verification while performing key tasks like place and route, CTS, and EM/IR analysis.

Key Responsibilities

Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
Setup and Synthesizing RTL
Timing closure through various methods and strategies
EM/IR Analysis
Place and Route, Clock Tree Synthesis, Floor-planning and Layout

Technical Overview

You will execute the full physical design flow including synthesis, physical verification, timing closure, place and route, clock tree synthesis, and floorplanning/layout, with EM/IR analysis. The role emphasizes RTL-to-tape-out ownership and requires TCL/PERL scripting and strong EDA tool proficiency.

Ideal Candidate

The ideal candidate is a senior physical IC design engineer with 8+ years of full physical design cycle experience from RTL to tape-out. They have hands-on expertise in timing closure, place and route, clock tree synthesis, and EM/IR analysis, along with strong scripting skills in TCL/PERL and proficiency with EDA tools. This person can communicate clearly and collaborate closely with RTL engineers and must be able to work in person at the San Jose site.

Must-Have Skills

TCL/PERL ScriptingProficiency in related EDA ToolsFull physical design cycle experience: RTL to Tape-outExcellent verbal and written communication skillsExecution of Physical DesignSynthesisPhysical Verificationand Timing ClosureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and Layout

Tools & Platforms

EDA ToolsTCLPERL Scripting

Required Skills

Physical DesignSynthesisPhysical VerificationTiming ClosureSetup and Synthesizing RTLEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and LayoutFlow and Methodology DevelopmentTCL/PERL ScriptingEDA ToolsRTL to Tape-out

Hard Skills

Physical DesignSynthesisPhysical VerificationTiming ClosureSetup and Synthesizing RTLTiming closureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planningLayoutFlow and Methodology DevelopmentTCLPERL ScriptingEDA ToolsRTL to Tape-outIC DesignFloorplanning and Layout

Soft Skills

Excellent verbal and written communication skillsCollaborating with IC Design RTL Engineers

Industry & Role

Industry Manufacturing

Job Function Own physical IC design execution from RTL to tape-out, ensuring timing closure and sign-off readiness

Role Subtype Physical Design Engineer

Tech Domains VMware

Keywords for Your Resume

Physical IC Design EngineerPhysical DesignSynthesisPhysical VerificationTiming ClosureRTL to Tape-outTape-outEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planning and LayoutTCLPERLPERL ScriptingTCL/PERL ScriptingEDA ToolsFlow and Methodology DevelopmentIC Design RTL EngineersTiming closureMust work in personSan Jose siteFloor-planning

Deal Breakers

Must work in person at the San Jose site: no remote work allowed, TCL/PERL Scripting required, Full physical design cycle experience: RTL to Tape-out required, Bachelor's degree required in Electrical Engineering or Electronics Engineering, 8+ years of relevant experience required

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