Position Details

Salary $141K – $226K USD / year

Type Not Specified

Experience senior

Exp. Years 12+ years

Education Bachelor's degree in Electrical Engineering or Electronics Engineering

Category Engineering (Non-Software)

About this role

This role involves leading the physical design and reliability testing of RF semiconductor devices, ensuring performance and long-term stability from RTL to tape-out.

Key Responsibilities

Execute physical design and verification
Manage RTL to Tape-out process
Conduct RF and IR testing
Lead failure analysis
Collaborate with R&D teams

Technical Overview

The technical environment includes RTL design, physical verification, RF testing, IR thermal imaging, and EDA tools, with a focus on semiconductor device physics and reliability.

Ideal Candidate

The ideal candidate is a senior semiconductor engineer with over 12 years of experience in physical design, RTL to Tape-out processes, and RF testing. They are proficient with EDA tools and have a strong background in device physics and reliability testing.

Must-Have Skills

Full physical design cycle experienceProficiency in TCL and PERL scriptingExperience with EDA toolsIn-depth knowledge of RTL to Tape-out process

Nice-to-Have Skills

Experience with RF and Power ElectronicsKnowledge of Semiconductor Device PhysicsRF TestingFailure Analysis

Tools & Platforms

EDA ToolsIR thermal imaging instrumentsQFI (Quantum Focus Instruments)

Required Skills

Physical DesignRTLSynthesisPhysical VerificationTiming ClosureEM/IR AnalysisPlace and RouteClock Tree SynthesisLayoutEDA ToolsRF TestingPower ElectronicsSemiconductor Device Physics

Hard Skills

Physical DesignRTLSynthesisPhysical VerificationTiming ClosureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planningLayoutTCLPERLEDA Tools

Soft Skills

Verbal communicationWritten communicationCollaborationProblem-solving

Industry & Role

Industry Semiconductor / Electronics

Job Function Semiconductor physical design and reliability engineering

Keywords for Your Resume

Physical DesignRTLSynthesisPhysical VerificationTiming ClosureEM/IR AnalysisPlace and RouteClock Tree SynthesisFloor-planningLayoutEDA ToolsRF TestingPower ElectronicsSemiconductor Device PhysicsTape-outIR Thermal Imaging

Deal Breakers

Less than 12 years of relevant experience, Lack of proficiency in RTL and EDA tools, No experience with RF or Power Electronics, Inability to work on-site at San Jose

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