Post-Silicon Systems Software Validation Engineer, Annapurna Labs

You will lead and own critical validation for next-generation machine learning accelerators, spanning early design validation through emulation, silicon bring-up, and post-silicon validation. The role includes developing validation strategies and test plans, collaborating with multiple hardware and software teams, and supporting production systems in AWS data centers.

• Develop comprehensive validation strategies and new methodologies to improve validation coverage and time to root cause.
• Lead detailed test plans covering functional, performance, power, and stress testing.
• Collaborate with architecture, RTL design, design verification, firmware, and software teams.
• Drive validation across the lifecycle from early design validation through emulation and silicon bring-up to post-silicon validation.
• Mentor and provide direction to junior validation engineers.

The role focuses on silicon and system validation across the hardware vertical stack, including high-speed components (HBM, PCIe) and system-to-system interfaces. You will apply RTL simulation using SystemVerilog/UVM with tools like VCS, Questa, and Xcelium, and use emulation platforms such as Palladium, Zebu, and Veloce through silicon failure analysis and debug, with optional cloud/CI/CD and firmware involvement (BIOS, BMC, drivers).

The ideal candidate is a mid-level Validation Engineer with strong programming skills and hands-on experience across the full silicon validation lifecycle, from RTL simulation through emulation and post-silicon debug. They have deep knowledge of computer architecture and chip/system validation methodologies, and practical experience with tools such as SystemVerilog/UVM, VCS, Questa, Xcelium, and emulation platforms like Palladium, Zebu, or Veloce. Bonus experience includes cloud infrastructure and CI/CD, plus firmware testing or development involving BIOS, BMC, and drivers.